afa8862328
a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
327 lines
11 KiB
C
327 lines
11 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SPECIALREG_H_
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#define _MACHINE_SPECIALREG_H_
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/*
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* Bits in 386 special registers:
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*/
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#define CR0_PE 0x00000001 /* Protected mode Enable */
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#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
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#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
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#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
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#ifdef notused
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#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
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#endif
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#define CR0_PG 0x80000000 /* PaGing enable */
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/*
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* Bits in 486 special registers:
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*/
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#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
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#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
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all modes) */
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#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
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#define CR0_NW 0x20000000 /* Not Write-through */
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#define CR0_CD 0x40000000 /* Cache Disable */
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/*
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* Bits in PPro special registers
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*/
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#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
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#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
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#define CR4_TSD 0x00000004 /* Time stamp disable */
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#define CR4_DE 0x00000008 /* Debugging extensions */
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#define CR4_PSE 0x00000010 /* Page size extensions */
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#define CR4_PAE 0x00000020 /* Physical address extension */
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#define CR4_MCE 0x00000040 /* Machine check enable */
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#define CR4_PGE 0x00000080 /* Page global enable */
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#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
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#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
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#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
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/*
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* Bits in AMD64 special registers. EFER is 64 bits wide.
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*/
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#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
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#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
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#define EFER_LMA 0x000000400 /* Long mode active (R) */
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#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
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/*
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* CPUID instruction features register
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*/
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#define CPUID_FPU 0x00000001
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#define CPUID_VME 0x00000002
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#define CPUID_DE 0x00000004
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#define CPUID_PSE 0x00000008
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#define CPUID_TSC 0x00000010
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#define CPUID_MSR 0x00000020
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#define CPUID_PAE 0x00000040
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#define CPUID_MCE 0x00000080
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#define CPUID_CX8 0x00000100
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#define CPUID_APIC 0x00000200
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#define CPUID_B10 0x00000400
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#define CPUID_SEP 0x00000800
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#define CPUID_MTRR 0x00001000
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#define CPUID_PGE 0x00002000
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#define CPUID_MCA 0x00004000
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#define CPUID_CMOV 0x00008000
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#define CPUID_PAT 0x00010000
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#define CPUID_PSE36 0x00020000
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#define CPUID_PSN 0x00040000
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#define CPUID_CLFSH 0x00080000
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#define CPUID_B20 0x00100000
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#define CPUID_DS 0x00200000
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#define CPUID_ACPI 0x00400000
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#define CPUID_MMX 0x00800000
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#define CPUID_FXSR 0x01000000
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#define CPUID_SSE 0x02000000
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#define CPUID_XMM 0x02000000
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#define CPUID_SSE2 0x04000000
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#define CPUID_SS 0x08000000
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#define CPUID_HTT 0x10000000
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#define CPUID_TM 0x20000000
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#define CPUID_B30 0x40000000
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#define CPUID_PBE 0x80000000
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/*
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* CPUID instruction 1 ebx info
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*/
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#define CPUID_BRAND_INDEX 0x000000ff
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#define CPUID_CLFUSH_SIZE 0x0000ff00
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#define CPUID_HTT_CORES 0x00ff0000
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#define CPUID_LOCAL_APIC_ID 0xff000000
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/*
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* Model-specific registers for the i386 family
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*/
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#define MSR_P5_MC_ADDR 0x000
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#define MSR_P5_MC_TYPE 0x001
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#define MSR_TSC 0x010
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_SYSENTER_CS 0x174
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#define MSR_SYSENTER_ESP 0x175
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#define MSR_SYSENTER_EIP 0x176
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRVarBase 0x200
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#define MSR_MTRR64kBase 0x250
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#define MSR_MTRR16kBase 0x258
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#define MSR_MTRR4kBase 0x268
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#define MSR_PAT 0x277
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC4_CTL 0x40c
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#define MSR_MC4_STATUS 0x40d
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#define MSR_MC4_ADDR 0x40e
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#define MSR_MC4_MISC 0x40f
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#define MSR_MC3_CTL 0x410
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#define MSR_MC3_STATUS 0x411
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#define MSR_MC3_ADDR 0x412
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#define MSR_MC3_MISC 0x413
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/*
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* Constants related to MTRRs
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*/
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#define MTRR_N64K 8 /* numbers of fixed-size entries */
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#define MTRR_N16K 16
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#define MTRR_N4K 64
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/* Performance Control Register (5x86 only). */
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#define PCR0 0x20
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#define PCR0_RSTK 0x01 /* Enables return stack */
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#define PCR0_BTB 0x02 /* Enables branch target buffer */
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#define PCR0_LOOP 0x04 /* Enables loop */
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#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
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serialize pipe. */
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#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
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#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
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#define PCR0_LSSER 0x80 /* Disable reorder */
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/* Device Identification Registers */
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#define DIR0 0xfe
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#define DIR1 0xff
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/*
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* The following four 3-byte registers control the non-cacheable regions.
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* These registers must be written as three separate bytes.
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*
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* NCRx+0: A31-A24 of starting address
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* NCRx+1: A23-A16 of starting address
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* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
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*
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* The non-cacheable region's starting address must be aligned to the
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* size indicated by the NCR_SIZE_xx field.
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*/
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#define NCR1 0xc4
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#define NCR2 0xc7
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#define NCR3 0xca
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#define NCR4 0xcd
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#define NCR_SIZE_0K 0
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#define NCR_SIZE_4K 1
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#define NCR_SIZE_8K 2
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#define NCR_SIZE_16K 3
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#define NCR_SIZE_32K 4
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#define NCR_SIZE_64K 5
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#define NCR_SIZE_128K 6
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#define NCR_SIZE_256K 7
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#define NCR_SIZE_512K 8
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#define NCR_SIZE_1M 9
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#define NCR_SIZE_2M 10
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#define NCR_SIZE_4M 11
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#define NCR_SIZE_8M 12
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#define NCR_SIZE_16M 13
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#define NCR_SIZE_32M 14
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#define NCR_SIZE_4G 15
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/*
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* The address region registers are used to specify the location and
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* size for the eight address regions.
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*
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* ARRx + 0: A31-A24 of start address
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* ARRx + 1: A23-A16 of start address
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* ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
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*/
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#define ARR0 0xc4
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#define ARR1 0xc7
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#define ARR2 0xca
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#define ARR3 0xcd
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#define ARR4 0xd0
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#define ARR5 0xd3
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#define ARR6 0xd6
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#define ARR7 0xd9
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#define ARR_SIZE_0K 0
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#define ARR_SIZE_4K 1
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#define ARR_SIZE_8K 2
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#define ARR_SIZE_16K 3
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#define ARR_SIZE_32K 4
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#define ARR_SIZE_64K 5
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#define ARR_SIZE_128K 6
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#define ARR_SIZE_256K 7
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#define ARR_SIZE_512K 8
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#define ARR_SIZE_1M 9
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#define ARR_SIZE_2M 10
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#define ARR_SIZE_4M 11
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#define ARR_SIZE_8M 12
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#define ARR_SIZE_16M 13
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#define ARR_SIZE_32M 14
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#define ARR_SIZE_4G 15
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/*
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* The region control registers specify the attributes associated with
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* the ARRx addres regions.
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*/
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#define RCR0 0xdc
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#define RCR1 0xdd
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#define RCR2 0xde
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#define RCR3 0xdf
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#define RCR4 0xe0
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#define RCR5 0xe1
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#define RCR6 0xe2
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#define RCR7 0xe3
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#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
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#define RCR_RCE 0x01 /* Enables caching for ARR7. */
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#define RCR_WWO 0x02 /* Weak write ordering. */
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#define RCR_WL 0x04 /* Weak locking. */
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#define RCR_WG 0x08 /* Write gathering. */
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#define RCR_WT 0x10 /* Write-through. */
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#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
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/* AMD Write Allocate Top-Of-Memory and Control Register */
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#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
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#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
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#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
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/* X86-64 MSR's */
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#define MSR_EFER 0xc0000080 /* extended features */
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#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
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#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
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#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
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#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
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#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
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#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
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#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
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#define MSR_PERFEVSEL0 0xc0010000
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#define MSR_PERFEVSEL1 0xc0010001
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#define MSR_PERFEVSEL2 0xc0010002
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#define MSR_PERFEVSEL3 0xc0010003
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#undef MSR_PERFCTR0
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#undef MSR_PERFCTR1
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#define MSR_PERFCTR0 0xc0010004
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#define MSR_PERFCTR1 0xc0010005
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#define MSR_PERFCTR2 0xc0010006
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#define MSR_PERFCTR3 0xc0010007
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#define MSR_SYSCFG 0xc0010010
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#define MSR_IORRBASE0 0xc0010016
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#define MSR_IORRMASK0 0xc0010017
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#define MSR_IORRBASE1 0xc0010018
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#define MSR_IORRMASK1 0xc0010019
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#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
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#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
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#endif /* !_MACHINE_SPECIALREG_H_ */
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