Davide Italiano f39e915e19 Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D). ... Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine. Approved by: gnn (mentor) MFC after: 3 days		2012-06-17 13:48:39 +00:00
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hwpmc_amd.c
hwpmc_amd.h
hwpmc_arm.c
hwpmc_core.c
hwpmc_core.h
hwpmc_ia64.c
hwpmc_intel.c
hwpmc_logging.c
hwpmc_mips24k.c
hwpmc_mips.c
hwpmc_mod.c
hwpmc_octeon.c
hwpmc_pentium.c
hwpmc_pentium.h
hwpmc_piv.c
hwpmc_piv.h
hwpmc_powerpc.c
hwpmc_ppro.c
hwpmc_ppro.h
hwpmc_soft.c
hwpmc_soft.h
hwpmc_sparc64.c
hwpmc_tsc.c
hwpmc_tsc.h
hwpmc_uncore.c
hwpmc_uncore.h
hwpmc_x86.c
hwpmc_xscale.c
hwpmc_xscale.h
pmc_events.h