750 lines
29 KiB
C
750 lines
29 KiB
C
/*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __AL_SERDES_INTERNAL_REGS_H__
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#define __AL_SERDES_INTERNAL_REGS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*******************************************************************************
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* Per lane register fields
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******************************************************************************/
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/*
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* RX and TX lane hard reset
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* 0 - Hard reset is asserted
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* 1 - Hard reset is de-asserted
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*/
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK 0x01
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT 0x00
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT 0x01
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/*
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* RX and TX lane hard reset control
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* 0 - Hard reset is taken from the interface pins
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* 1 - Hard reset is taken from registers
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*/
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK 0x02
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE 0x00
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#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS 0x02
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/* RX lane power state control */
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM 3
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK 0x1f
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD 0x01
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2 0x02
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1 0x04
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S 0x08
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#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0 0x10
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/* TX lane power state control */
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM 4
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK 0x1f
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD 0x01
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2 0x02
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1 0x04
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S 0x08
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#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0 0x10
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/* RX lane word width */
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM 5
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK 0x07
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8 0x00
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10 0x01
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16 0x02
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 0x03
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32 0x04
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#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40 0x05
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/* TX lane word width */
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM 5
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK 0x70
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8 0x00
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10 0x10
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16 0x20
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20 0x30
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32 0x40
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#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40 0x50
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/* RX lane rate select */
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM 6
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK 0x07
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8 0x00
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4 0x01
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2 0x02
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#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1 0x03
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/* TX lane rate select */
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM 6
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK 0x70
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8 0x00
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4 0x10
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2 0x20
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#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1 0x30
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/*
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* PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
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* to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
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* partial equalized RX signal out the transmit IO pins
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*/
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#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM 7
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#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN 0x10
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/*
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* PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
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* transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
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* the TX serializer output into the CDR
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*/
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#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM 7
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#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN 0x20
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/*
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* PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
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* RX pads). Serial IO loopback from the transmit lane IO pins to the receive
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* lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
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* the RX IO pins
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*/
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#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM 7
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#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN 0x40
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/*
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* PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
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* receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
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* Disables loopback 1 - Loops back the 20-bit receive data port to the
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* transmitter
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*/
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#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM 7
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#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN 0x80
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/*
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* PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
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* Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
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* - Selects CDR clock for transmit
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*/
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#define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM 7
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#define SERDES_IREG_FLD_LB_CDRCLK2TXEN 0x01
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/* Receive lane BIST enable. Active High */
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#define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM 8
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#define SERDES_IREG_FLD_PCSRXBIST_EN 0x01
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/* TX lane BIST enable. Active High */
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#define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM 8
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#define SERDES_IREG_FLD_PCSTXBIST_EN 0x02
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/*
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* RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
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* the test has completed, and will remain high until a new test is initiated
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*/
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#define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM 8
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#define SERDES_IREG_FLD_RXBIST_DONE 0x04
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/*
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* RX BIST error count overflow indicator. Indicates an overflow in the number
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* of byte errors identified during the course of the test. This word is stable
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* to sample when *_DONE_* signal has asserted
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*/
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#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM 8
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#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW 0x08
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/*
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* RX BIST locked indicator 0 - Indicates BIST is not word locked and error
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* comparisons have not begun yet 1 - Indicates BIST is word locked and error
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* comparisons have begun
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*/
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#define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM 8
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#define SERDES_IREG_FLD_RXBIST_RXLOCKED 0x10
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/*
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* RX BIST error count word. Indicates the number of byte errors identified
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* during the course of the test. This word is stable to sample when *_DONE_*
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* signal has asserted
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*/
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#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM 9
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#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM 10
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/* Tx params */
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#define SERDES_IREG_TX_DRV_1_REG_NUM 21
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#define SERDES_IREG_TX_DRV_1_HLEV_MASK 0x7
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#define SERDES_IREG_TX_DRV_1_HLEV_SHIFT 0
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#define SERDES_IREG_TX_DRV_1_LEVN_MASK 0xf8
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#define SERDES_IREG_TX_DRV_1_LEVN_SHIFT 3
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#define SERDES_IREG_TX_DRV_2_REG_NUM 22
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#define SERDES_IREG_TX_DRV_2_LEVNM1_MASK 0xf
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#define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT 0
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#define SERDES_IREG_TX_DRV_2_LEVNM2_MASK 0x30
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#define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT 4
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#define SERDES_IREG_TX_DRV_3_REG_NUM 23
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#define SERDES_IREG_TX_DRV_3_LEVNP1_MASK 0x7
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#define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT 0
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#define SERDES_IREG_TX_DRV_3_SLEW_MASK 0x18
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#define SERDES_IREG_TX_DRV_3_SLEW_SHIFT 3
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/* Rx params */
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#define SERDES_IREG_RX_CALEQ_1_REG_NUM 24
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#define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK 0x7
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#define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT 0
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/* DFE post-shaping tap 3dB frequency */
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#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK 0x38
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#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT 3
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#define SERDES_IREG_RX_CALEQ_2_REG_NUM 25
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/* DFE post-shaping tap gain */
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#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK 0x7
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#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT 0
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/* DFE first tap gain control */
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#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK 0x78
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#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT 3
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#define SERDES_IREG_RX_CALEQ_3_REG_NUM 26
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#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK 0xf
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#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT 0
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#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK 0xf0
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#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT 4
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#define SERDES_IREG_RX_CALEQ_4_REG_NUM 27
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#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK 0xf
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#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT 0
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#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK 0x70
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#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT 4
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#define SERDES_IREG_RX_CALEQ_5_REG_NUM 28
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#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK 0x7
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#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT 0
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#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK 0xf8
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#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT 3
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/* RX lane best eye point measurement result */
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#define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM 29
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#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM 30
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#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK 0x3F
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/*
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* Adaptive RX Equalization enable
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* 0 - Disables adaptive RX equalization.
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* 1 - Enables adaptive RX equalization.
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*/
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#define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM 31
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#define SERDES_IREG_FLD_PCSRXEQ_START (1 << 0)
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/*
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* Enables an eye diagram measurement
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* within the PHY.
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* 0 - Disables eye diagram measurement
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* 1 - Enables eye diagram measurement
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*/
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM 31
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START (1 << 1)
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/*
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* RX lane single roam eye point measurement start signal.
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* If asserted, single measurement at fix XADJUST and YADJUST is started.
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*/
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#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM 31
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#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START (1 << 2)
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/*
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* PHY Eye diagram measurement status
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* signal
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* 0 - Indicates eye diagram results are not
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* valid for sampling
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* 1 - Indicates eye diagram is complete and
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* results are valid for sampling
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*/
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM 32
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE (1 << 0)
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/*
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* Eye diagram error signal. Indicates if the
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* measurement was invalid because the eye
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* diagram was interrupted by the link entering
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* electrical idle.
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* 0 - Indicates eye diagram is valid
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* 1- Indicates an error occurred, and the eye
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* diagram measurement should be re-run
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*/
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM 32
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR (1 << 1)
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/*
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* PHY Adaptive Equalization status
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* 0 - Indicates Adaptive Equalization results are not valid for sampling
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* 1 - Indicates Adaptive Equalization is complete and results are valid for
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* sampling
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*/
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#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM 32
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#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE (1 << 2)
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/*
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*
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* PHY Adaptive Equalization Status Signal
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* 0 – Indicates adaptive equalization results
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* are not valid for sampling
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* 1 – Indicates adaptive equalization is
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* complete and results are valid for sampling.
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*/
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#define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM 32
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#define SERDES_IREG_FLD_RXEQ_DONE (1 << 3)
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/*
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* 7-bit eye diagram time adjust control
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* - 6-bits per UI
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* - spans 2 UI
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*/
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#define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM 33
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/* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
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#define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM 34
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/*
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* Eye diagram status signal. Safe for
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* sampling when *DONE* signal has
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* asserted
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* 14'h0000 - Completely Closed Eye
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* 14'hFFFF - Completely Open Eye
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*/
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM 35
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE 0xFF
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT 0
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM 36
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE 0x3F
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#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT 0
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/*
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* RX lane single roam eye point measurement result.
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* If 0, eye is open at current XADJUST and YADJUST settings.
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*/
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#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM 37
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#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM 38
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/*
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* Override enable for CDR lock to reference clock
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* 0 - CDR is always locked to reference
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* 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
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* depending on the incoming signal and ppm status)
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*/
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#define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM 39
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#define SERDES_IREG_FLD_RXLOCK2REF_OVREN (1 << 1)
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/*
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* Selects Eye to capture based on edge
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* 0 - Capture 1st Eye in Eye Diagram
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* 1 - Capture 2nd Eye in Eye Diagram measurement
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*/
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#define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM 39
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#define SERDES_IREG_FLD_RXROAM_XORBITSEL (1 << 2)
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#define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST 0
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#define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND (1 << 2)
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/*
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* RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
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*/
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#define SERDES_IREG_FLD_RXRANDET_REG_NUM 41
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#define SERDES_IREG_FLD_RXRANDET_STAT 0x20
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/*
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* RX data polarity inversion control:
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* 1'b0: no inversion
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* 1'b1: invert polarity
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*/
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#define SERDES_IREG_FLD_POLARITY_RX_REG_NUM 46
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#define SERDES_IREG_FLD_POLARITY_RX_INV (1 << 0)
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/*
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* TX data polarity inversion control:
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* 1'b0: no inversion
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* 1'b1: invert polarity
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*/
|
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#define SERDES_IREG_FLD_POLARITY_TX_REG_NUM 46
|
||
#define SERDES_IREG_FLD_POLARITY_TX_INV (1 << 1)
|
||
|
||
/* LANEPCSPSTATE* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN (1 << 0)
|
||
|
||
/* LB* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_LB_LOCWREN (1 << 1)
|
||
|
||
/* PCSRX* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_PCSRX_LOCWREN (1 << 4)
|
||
|
||
/* PCSRXBIST* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN (1 << 5)
|
||
|
||
/* PCSRXEQ* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN (1 << 6)
|
||
|
||
/* PCSTX* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM 85
|
||
#define SERDES_IREG_FLD_PCSTX_LOCWREN (1 << 7)
|
||
|
||
/*
|
||
* group registers:
|
||
* SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
|
||
* SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
|
||
* SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
|
||
*/
|
||
#define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM 86
|
||
|
||
/* PCSTXBIST* override enable (Active low) */
|
||
#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM 86
|
||
#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN (1 << 0)
|
||
|
||
/* Override RX_CALCEQ through the internal registers (Active low) */
|
||
#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM 86
|
||
#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN (1 << 3)
|
||
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM 86
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN (1 << 4)
|
||
|
||
|
||
/* RXCALROAMEYEMEASIN* override enable - Active Low */
|
||
#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM 86
|
||
#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN (1 << 6)
|
||
|
||
/* RXCALROAMXADJUST* override enable - Active Low */
|
||
#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM 86
|
||
#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN (1 << 7)
|
||
|
||
/* RXCALROAMYADJUST* override enable - Active Low */
|
||
#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN (1 << 0)
|
||
|
||
/* RXCDRCALFOSC* override enable. Active Low */
|
||
#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN (1 << 1)
|
||
|
||
/* Over-write enable for RXEYEDIAGFSM_INITXVAL */
|
||
#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN (1 << 2)
|
||
|
||
/* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
|
||
#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN (1 << 3)
|
||
|
||
/* TXCALTCLKDUTY* override enable. Active Low */
|
||
#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN (1 << 4)
|
||
|
||
/* Override TX_DRV through the internal registers (Active low) */
|
||
#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM 87
|
||
#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN (1 << 5)
|
||
|
||
/*******************************************************************************
|
||
* Common lane register fields - PMA
|
||
******************************************************************************/
|
||
/*
|
||
* Common lane hard reset control
|
||
* 0 - Hard reset is taken from the interface pins
|
||
* 1 - Hard reset is taken from registers
|
||
*/
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM 2
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK 0x01
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE 0x00
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS 0x01
|
||
|
||
/*
|
||
* Common lane hard reset
|
||
* 0 - Hard reset is asserted
|
||
* 1 - Hard reset is de-asserted
|
||
*/
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM 2
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK 0x02
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT 0x00
|
||
#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT 0x02
|
||
|
||
/* Synth power state control */
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM 3
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK 0x1f
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD 0x01
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2 0x02
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1 0x04
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S 0x08
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0 0x10
|
||
|
||
/* Transmit datapath FIFO enable (Active High) */
|
||
#define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM 8
|
||
#define SERDES_IREG_FLD_CMNPCS_TXENABLE (1 << 2)
|
||
|
||
/*
|
||
* RX lost of signal detector enable
|
||
* - 0 - disable
|
||
* - 1 - enable
|
||
*/
|
||
#define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM 13
|
||
#define SERDES_IREG_FLD_RXLOSDET_ENABLE AL_BIT(4)
|
||
|
||
/* Signal Detect Threshold Level */
|
||
#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM 15
|
||
#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
|
||
|
||
/* LOS Detect Threshold Level */
|
||
#define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM 15
|
||
#define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
|
||
#define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT 3
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM 30
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK 0x7f
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM 31
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK 0x7f
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM 32
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK 0xff
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM 33
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK 0x1
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM 33
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK 0x3e
|
||
#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT 1
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM 34
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK 0xff
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM 35
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK 0x1
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM 35
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK 0x3e
|
||
#define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT 1
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM 36
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK 0xff
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM 37
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK 0x7
|
||
#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM 43
|
||
#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK 0x7
|
||
#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num) (56 + (byte_num))
|
||
#define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES 10
|
||
|
||
/*
|
||
* Selects the transmit BIST mode:
|
||
* 0 - Uses the 80-bit internal memory pattern (w/ OOB)
|
||
* 1 - Uses a 27 PRBS pattern
|
||
* 2 - Uses a 223 PRBS pattern
|
||
* 3 - Uses a 231 PRBS pattern
|
||
* 4 - Uses a 1010 clock pattern
|
||
* 5 and above - Reserved
|
||
*/
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM 80
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK 0x07
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER 0x00
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7 0x01
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23 0x02
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31 0x03
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010 0x04
|
||
|
||
/* Single-Bit error injection enable (on posedge) */
|
||
#define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM 80
|
||
#define SERDES_IREG_FLD_TXBIST_BITERROR_EN 0x20
|
||
|
||
/* CMNPCIEGEN3* override enable (Active Low) */
|
||
#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM 95
|
||
#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN (1 << 2)
|
||
|
||
/* CMNPCS* override enable (Active Low) */
|
||
#define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM 95
|
||
#define SERDES_IREG_FLD_CMNPCS_LOCWREN (1 << 3)
|
||
|
||
/* CMNPCSBIST* override enable (Active Low) */
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM 95
|
||
#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN (1 << 4)
|
||
|
||
/* CMNPCSPSTATE* override enable (Active Low) */
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM 95
|
||
#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN (1 << 5)
|
||
|
||
/* PCS_EN* override enable (Active Low) */
|
||
#define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM 96
|
||
#define SERDES_IREG_FLD_PCS_LOCWREN (1 << 3)
|
||
|
||
/* Eye diagram sample count */
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM 150
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK 0xff
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM 151
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK 0xff
|
||
#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT 0
|
||
|
||
/* override control */
|
||
#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM 230
|
||
#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN 1 << 0
|
||
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM 623
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK 0xff
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM 624
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK 0xff
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT 0
|
||
|
||
/* X and Y coefficient return value */
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM 626
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK 0x0F
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT 0
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK 0xF0
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT 4
|
||
|
||
/* X coarse scan step */
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM 627
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK 0x7F
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT 0
|
||
|
||
/* X fine scan step */
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM 628
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK 0x7F
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT 0
|
||
|
||
/* Y coarse scan step */
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM 629
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK 0x0F
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT 0
|
||
|
||
/* Y fine scan step */
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM 630
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK 0x0F
|
||
#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM 157
|
||
|
||
#define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM 158
|
||
|
||
#define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM 159
|
||
|
||
#define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM 160
|
||
|
||
#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM 163
|
||
|
||
#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM 164
|
||
|
||
/*******************************************************************************
|
||
* Common lane register fields - PCS
|
||
******************************************************************************/
|
||
#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM 3
|
||
#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
|
||
#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT 4
|
||
|
||
#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM 6
|
||
#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA AL_BIT(2)
|
||
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM 18
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK 0x1F
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM 19
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK 0x7C
|
||
#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT 2
|
||
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM 20
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK 0x1F
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM 21
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK 0x7C
|
||
#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT 2
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM 22
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK 0x7f
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM 34
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK 0x7f
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM 23
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK 0xff
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM 22
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK 0x80
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT 7
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM 24
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK 0x3e
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT 1
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM 35
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK 0xff
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT 0
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM 34
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK 0x80
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT 7
|
||
|
||
#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM 36
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#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK 0x1f
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#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT 0
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM 37
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK 0xff
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT 0
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM 36
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK 0xe0
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#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT 5
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AL_serdes_REG_H */
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