091e8307d0
current context in the IPI_STOP handler so that we can get accurate stack traces of threads on other CPUs on these two archs like we do now on i386 and amd64. Tested on: alpha, sparc64
259 lines
6.0 KiB
C
259 lines
6.0 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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#define CPU_CLKSYNC 1
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#define CPU_INIT 2
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#define CPU_BOOTSTRAP 3
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#ifndef LOCORE
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#include <machine/intr_machdep.h>
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#include <machine/tte.h>
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#define IDR_BUSY (1<<0)
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#define IDR_NACK (1<<1)
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#define IPI_AST PIL_AST
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#define IPI_RENDEZVOUS PIL_RENDEZVOUS
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#define IPI_STOP PIL_STOP
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#define IPI_RETRIES 5000
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struct cpu_start_args {
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u_int csa_count;
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u_int csa_mid;
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u_int csa_state;
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vm_offset_t csa_pcpu;
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u_long csa_tick;
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u_long csa_ver;
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struct tte csa_ttes[PCPU_PAGES];
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};
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struct ipi_cache_args {
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u_int ica_mask;
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vm_paddr_t ica_pa;
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};
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struct ipi_tlb_args {
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u_int ita_mask;
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struct pmap *ita_pmap;
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u_long ita_start;
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u_long ita_end;
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};
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#define ita_va ita_start
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struct pcpu;
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extern struct pcb stoppcbs[];
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void cpu_mp_bootstrap(struct pcpu *pc);
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void cpu_mp_shutdown(void);
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void cpu_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2);
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void cpu_ipi_send(u_int mid, u_long d0, u_long d1, u_long d2);
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void ipi_selected(u_int cpus, u_int ipi);
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void ipi_all(u_int ipi);
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void ipi_all_but_self(u_int ipi);
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vm_offset_t mp_tramp_alloc(void);
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extern struct mtx ipi_mtx;
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extern struct ipi_cache_args ipi_cache_args;
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extern struct ipi_tlb_args ipi_tlb_args;
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extern vm_offset_t mp_tramp;
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extern char *mp_tramp_code;
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extern u_long mp_tramp_code_len;
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extern u_long mp_tramp_tlb_slots;
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extern u_long mp_tramp_func;
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extern void mp_startup(void);
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extern char tl_ipi_cheetah_dcache_page_inval[];
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extern char tl_ipi_spitfire_dcache_page_inval[];
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extern char tl_ipi_spitfire_icache_page_inval[];
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extern char tl_ipi_level[];
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extern char tl_ipi_tlb_context_demap[];
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extern char tl_ipi_tlb_page_demap[];
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extern char tl_ipi_tlb_range_demap[];
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#ifdef SMP
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#if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
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static __inline void *
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ipi_dcache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (smp_cpus == 1)
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return (NULL);
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ica = &ipi_cache_args;
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mtx_lock_spin(&ipi_mtx);
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ica->ica_mask = all_cpus;
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ica->ica_pa = pa;
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cpu_ipi_selected(PCPU_GET(other_cpus), 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_icache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (smp_cpus == 1)
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return (NULL);
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ica = &ipi_cache_args;
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mtx_lock_spin(&ipi_mtx);
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ica->ica_mask = all_cpus;
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ica->ica_pa = pa;
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cpu_ipi_selected(PCPU_GET(other_cpus), 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm)
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{
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struct ipi_tlb_args *ita;
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u_int cpus;
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if (smp_cpus == 1)
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return (NULL);
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if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
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return (NULL);
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus | PCPU_GET(cpumask);
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ita->ita_pmap = pm;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
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(u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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struct ipi_tlb_args *ita;
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u_int cpus;
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if (smp_cpus == 1)
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return (NULL);
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if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
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return (NULL);
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus | PCPU_GET(cpumask);
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ita->ita_pmap = pm;
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ita->ita_va = va;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
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{
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struct ipi_tlb_args *ita;
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u_int cpus;
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if (smp_cpus == 1)
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return (NULL);
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if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
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return (NULL);
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus | PCPU_GET(cpumask);
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ita->ita_pmap = pm;
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ita->ita_start = start;
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ita->ita_end = end;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap, (u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void
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ipi_wait(void *cookie)
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{
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volatile u_int *mask;
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if ((mask = cookie) != NULL) {
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atomic_clear_int(mask, PCPU_GET(cpumask));
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while (*mask != 0)
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;
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mtx_unlock_spin(&ipi_mtx);
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}
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}
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#endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
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#else
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static __inline void *
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ipi_dcache_page_inval(void *func, vm_paddr_t pa)
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{
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return (NULL);
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}
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static __inline void *
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ipi_icache_page_inval(void *func, vm_paddr_t pa)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
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{
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return (NULL);
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}
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static __inline void
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ipi_wait(void *cookie)
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{
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}
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#endif /* SMP */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_SMP_H_ */
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