718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
563 lines
18 KiB
C
563 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <dev/nxge/include/xgehal-fifo.h>
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#include <dev/nxge/include/xgehal-device.h>
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static xge_hal_status_e
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__hal_fifo_mempool_item_alloc(xge_hal_mempool_h mempoolh,
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void *memblock,
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int memblock_index,
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xge_hal_mempool_dma_t *dma_object,
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void *item,
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int index,
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int is_last,
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void *userdata)
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{
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int memblock_item_idx;
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xge_hal_fifo_txdl_priv_t *txdl_priv;
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xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)item;
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
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xge_assert(item);
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txdl_priv = (xge_hal_fifo_txdl_priv_t *) \
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__hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh,
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memblock_index,
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item,
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&memblock_item_idx);
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xge_assert(txdl_priv);
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/* pre-format HAL's TxDL's private */
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txdl_priv->dma_offset = (char*)item - (char*)memblock;
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txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
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txdl_priv->dma_handle = dma_object->handle;
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txdl_priv->memblock = memblock;
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txdl_priv->first_txdp = (xge_hal_fifo_txd_t *)item;
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txdl_priv->next_txdl_priv = NULL;
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txdl_priv->dang_txdl = NULL;
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txdl_priv->dang_frags = 0;
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txdl_priv->alloc_frags = 0;
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#ifdef XGE_DEBUG_ASSERT
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txdl_priv->dma_object = dma_object;
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#endif
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txdp->host_control = (u64)(ulong_t)txdl_priv;
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#ifdef XGE_HAL_ALIGN_XMIT
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txdl_priv->align_vaddr = NULL;
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txdl_priv->align_dma_addr = (dma_addr_t)0;
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#ifndef XGE_HAL_ALIGN_XMIT_ALLOC_RT
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{
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xge_hal_status_e status;
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if (fifo->config->alignment_size) {
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status =__hal_fifo_dtr_align_alloc_map(fifo, txdp);
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if (status != XGE_HAL_OK) {
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xge_debug_mm(XGE_ERR,
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"align buffer[%d] %d bytes, status %d",
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index,
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fifo->align_size,
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status);
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return status;
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}
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}
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}
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#endif
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#endif
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if (fifo->channel.dtr_init) {
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fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index,
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fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL);
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}
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return XGE_HAL_OK;
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}
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static xge_hal_status_e
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__hal_fifo_mempool_item_free(xge_hal_mempool_h mempoolh,
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void *memblock,
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int memblock_index,
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xge_hal_mempool_dma_t *dma_object,
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void *item,
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int index,
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int is_last,
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void *userdata)
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{
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int memblock_item_idx;
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xge_hal_fifo_txdl_priv_t *txdl_priv;
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#ifdef XGE_HAL_ALIGN_XMIT
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
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#endif
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xge_assert(item);
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txdl_priv = (xge_hal_fifo_txdl_priv_t *) \
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__hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh,
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memblock_index,
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item,
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&memblock_item_idx);
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xge_assert(txdl_priv);
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#ifdef XGE_HAL_ALIGN_XMIT
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if (fifo->config->alignment_size) {
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if (txdl_priv->align_dma_addr != 0) {
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xge_os_dma_unmap(fifo->channel.pdev,
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txdl_priv->align_dma_handle,
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txdl_priv->align_dma_addr,
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fifo->align_size,
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XGE_OS_DMA_DIR_TODEVICE);
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txdl_priv->align_dma_addr = 0;
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}
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if (txdl_priv->align_vaddr != NULL) {
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xge_os_dma_free(fifo->channel.pdev,
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txdl_priv->align_vaddr,
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fifo->align_size,
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&txdl_priv->align_dma_acch,
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&txdl_priv->align_dma_handle);
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txdl_priv->align_vaddr = NULL;
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}
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}
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#endif
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return XGE_HAL_OK;
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}
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xge_hal_status_e
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__hal_fifo_open(xge_hal_channel_h channelh, xge_hal_channel_attr_t *attr)
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{
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xge_hal_device_t *hldev;
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xge_hal_status_e status;
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
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xge_hal_fifo_queue_t *queue;
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int i, txdl_size, max_arr_index, mid_point;
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xge_hal_dtr_h dtrh;
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hldev = (xge_hal_device_t *)fifo->channel.devh;
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fifo->config = &hldev->config.fifo;
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queue = &fifo->config->queue[attr->post_qid];
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#if defined(XGE_HAL_TX_MULTI_RESERVE)
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xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev);
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#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
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xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh);
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#endif
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#if defined(XGE_HAL_TX_MULTI_POST)
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if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) {
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fifo->post_lock_ptr = &hldev->xena_post_lock;
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} else {
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xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev);
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fifo->post_lock_ptr = &fifo->channel.post_lock;
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}
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#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
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if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) {
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fifo->post_lock_ptr = &hldev->xena_post_lock;
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} else {
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xge_os_spin_lock_init_irq(&fifo->channel.post_lock,
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hldev->irqh);
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fifo->post_lock_ptr = &fifo->channel.post_lock;
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}
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#endif
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fifo->align_size =
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fifo->config->alignment_size * fifo->config->max_aligned_frags;
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/* Initializing the BAR1 address as the start of
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* the FIFO queue pointer and as a location of FIFO control
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* word. */
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fifo->hw_pair =
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(xge_hal_fifo_hw_pair_t *) (void *)(hldev->bar1 +
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(attr->post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET));
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/* apply "interrupts per txdl" attribute */
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fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_UTILZ;
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if (queue->intr) {
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fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_PER_LIST;
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}
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fifo->no_snoop_bits =
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(int)(XGE_HAL_TX_FIFO_NO_SNOOP(queue->no_snoop_bits));
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/*
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* FIFO memory management strategy:
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*
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* TxDL splitted into three independent parts:
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* - set of TxD's
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* - TxD HAL private part
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* - upper layer private part
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*
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* Adaptative memory allocation used. i.e. Memory allocated on
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* demand with the size which will fit into one memory block.
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* One memory block may contain more than one TxDL. In simple case
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* memory block size can be equal to CPU page size. On more
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* sophisticated OS's memory block can be contigious across
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* several pages.
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*
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* During "reserve" operations more memory can be allocated on demand
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* for example due to FIFO full condition.
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*
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* Pool of memory memblocks never shrinks except __hal_fifo_close
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* routine which will essentially stop channel and free the resources.
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*/
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/* TxDL common private size == TxDL private + ULD private */
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fifo->priv_size = sizeof(xge_hal_fifo_txdl_priv_t) +
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attr->per_dtr_space;
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fifo->priv_size = ((fifo->priv_size + __xge_os_cacheline_size -1) /
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__xge_os_cacheline_size) *
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__xge_os_cacheline_size;
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/* recompute txdl size to be cacheline aligned */
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fifo->txdl_size = fifo->config->max_frags * sizeof(xge_hal_fifo_txd_t);
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txdl_size = ((fifo->txdl_size + __xge_os_cacheline_size - 1) /
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__xge_os_cacheline_size) * __xge_os_cacheline_size;
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if (fifo->txdl_size != txdl_size)
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xge_debug_fifo(XGE_ERR, "cacheline > 128 ( ?? ): %d, %d, %d, %d",
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fifo->config->max_frags, fifo->txdl_size, txdl_size,
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__xge_os_cacheline_size);
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fifo->txdl_size = txdl_size;
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/* since dtr_init() callback will be called from item_alloc(),
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* the same way channels userdata might be used prior to
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* channel_initialize() */
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fifo->channel.dtr_init = attr->dtr_init;
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fifo->channel.userdata = attr->userdata;
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fifo->txdl_per_memblock = fifo->config->memblock_size /
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fifo->txdl_size;
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fifo->mempool = __hal_mempool_create(hldev->pdev,
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fifo->config->memblock_size,
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fifo->txdl_size,
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fifo->priv_size,
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queue->initial,
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queue->max,
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__hal_fifo_mempool_item_alloc,
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__hal_fifo_mempool_item_free,
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fifo);
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if (fifo->mempool == NULL) {
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return XGE_HAL_ERR_OUT_OF_MEMORY;
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}
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status = __hal_channel_initialize(channelh, attr,
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(void **) __hal_mempool_items_arr(fifo->mempool),
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queue->initial, queue->max,
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fifo->config->reserve_threshold);
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if (status != XGE_HAL_OK) {
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__hal_fifo_close(channelh);
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return status;
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}
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xge_debug_fifo(XGE_TRACE,
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"DTR reserve_length:%d reserve_top:%d\n"
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"max_frags:%d reserve_threshold:%d\n"
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"memblock_size:%d alignment_size:%d max_aligned_frags:%d",
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fifo->channel.reserve_length, fifo->channel.reserve_top,
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fifo->config->max_frags, fifo->config->reserve_threshold,
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fifo->config->memblock_size, fifo->config->alignment_size,
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fifo->config->max_aligned_frags);
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#ifdef XGE_DEBUG_ASSERT
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for ( i = 0; i < fifo->channel.reserve_length; i++) {
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xge_debug_fifo(XGE_TRACE, "DTR before reversing index:%d"
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" handle:%p", i, fifo->channel.reserve_arr[i]);
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}
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#endif
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xge_assert(fifo->channel.reserve_length);
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/* reverse the FIFO dtr array */
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max_arr_index = fifo->channel.reserve_length - 1;
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max_arr_index -=fifo->channel.reserve_top;
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xge_assert(max_arr_index);
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mid_point = (fifo->channel.reserve_length - fifo->channel.reserve_top)/2;
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for (i = 0; i < mid_point; i++) {
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dtrh = fifo->channel.reserve_arr[i];
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fifo->channel.reserve_arr[i] =
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fifo->channel.reserve_arr[max_arr_index - i];
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fifo->channel.reserve_arr[max_arr_index - i] = dtrh;
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}
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#ifdef XGE_DEBUG_ASSERT
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for ( i = 0; i < fifo->channel.reserve_length; i++) {
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xge_debug_fifo(XGE_TRACE, "DTR after reversing index:%d"
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" handle:%p", i, fifo->channel.reserve_arr[i]);
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}
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#endif
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return XGE_HAL_OK;
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}
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void
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__hal_fifo_close(xge_hal_channel_h channelh)
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{
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
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xge_hal_device_t *hldev = (xge_hal_device_t *)fifo->channel.devh;
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if (fifo->mempool) {
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__hal_mempool_destroy(fifo->mempool);
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}
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__hal_channel_terminate(channelh);
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#if defined(XGE_HAL_TX_MULTI_RESERVE)
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xge_os_spin_lock_destroy(&fifo->channel.reserve_lock, hldev->pdev);
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#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
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xge_os_spin_lock_destroy_irq(&fifo->channel.reserve_lock, hldev->pdev);
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#endif
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if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
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#if defined(XGE_HAL_TX_MULTI_POST)
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xge_os_spin_lock_destroy(&fifo->channel.post_lock, hldev->pdev);
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#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
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xge_os_spin_lock_destroy_irq(&fifo->channel.post_lock,
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hldev->pdev);
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#endif
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}
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}
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void
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__hal_fifo_hw_initialize(xge_hal_device_h devh)
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{
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xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
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xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
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u64* tx_fifo_partitions[4];
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u64* tx_fifo_wrr[5];
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u64 tx_fifo_wrr_value[5];
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u64 val64, part0;
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int i;
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/* Tx DMA Initialization */
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tx_fifo_partitions[0] = &bar0->tx_fifo_partition_0;
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tx_fifo_partitions[1] = &bar0->tx_fifo_partition_1;
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tx_fifo_partitions[2] = &bar0->tx_fifo_partition_2;
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tx_fifo_partitions[3] = &bar0->tx_fifo_partition_3;
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tx_fifo_wrr[0] = &bar0->tx_w_round_robin_0;
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tx_fifo_wrr[1] = &bar0->tx_w_round_robin_1;
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tx_fifo_wrr[2] = &bar0->tx_w_round_robin_2;
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tx_fifo_wrr[3] = &bar0->tx_w_round_robin_3;
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tx_fifo_wrr[4] = &bar0->tx_w_round_robin_4;
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tx_fifo_wrr_value[0] = XGE_HAL_FIFO_WRR_0;
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tx_fifo_wrr_value[1] = XGE_HAL_FIFO_WRR_1;
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tx_fifo_wrr_value[2] = XGE_HAL_FIFO_WRR_2;
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tx_fifo_wrr_value[3] = XGE_HAL_FIFO_WRR_3;
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tx_fifo_wrr_value[4] = XGE_HAL_FIFO_WRR_4;
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/* Note: WRR calendar must be configured before the transmit
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* FIFOs are enabled! page 6-77 user guide */
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if (!hldev->config.rts_qos_en) {
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/* all zeroes for Round-Robin */
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for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) {
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xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0,
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tx_fifo_wrr[i]);
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}
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/* reset all of them but '0' */
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for (i=1; i < XGE_HAL_FIFO_MAX_PARTITION; i++) {
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xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL,
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tx_fifo_partitions[i]);
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}
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} else { /* Change the default settings */
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for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) {
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xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
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tx_fifo_wrr_value[i], tx_fifo_wrr[i]);
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}
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}
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/* configure only configured FIFOs */
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val64 = 0; part0 = 0;
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for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) {
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int reg_half = i % 2;
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int reg_num = i / 2;
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if (hldev->config.fifo.queue[i].configured) {
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int priority = hldev->config.fifo.queue[i].priority;
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val64 |=
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vBIT((hldev->config.fifo.queue[i].max-1),
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(((reg_half) * 32) + 19),
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13) | vBIT(priority, (((reg_half)*32) + 5), 3);
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}
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/* NOTE: do write operation for each second u64 half
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* or force for first one if configured number
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* is even */
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if (reg_half) {
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if (reg_num == 0) {
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/* skip partition '0', must write it once at
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* the end */
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part0 = val64;
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} else {
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xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
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val64, tx_fifo_partitions[reg_num]);
|
|
xge_debug_fifo(XGE_TRACE,
|
|
"fifo partition_%d at: "
|
|
"0x"XGE_OS_LLXFMT" is: 0x"XGE_OS_LLXFMT,
|
|
reg_num, (unsigned long long)(ulong_t)
|
|
tx_fifo_partitions[reg_num],
|
|
(unsigned long long)val64);
|
|
}
|
|
val64 = 0;
|
|
}
|
|
}
|
|
|
|
part0 |= BIT(0); /* to enable the FIFO partition. */
|
|
__hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)part0,
|
|
tx_fifo_partitions[0]);
|
|
xge_os_wmb();
|
|
__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(part0>>32),
|
|
tx_fifo_partitions[0]);
|
|
xge_debug_fifo(XGE_TRACE, "fifo partition_0 at: "
|
|
"0x"XGE_OS_LLXFMT" is: 0x"XGE_OS_LLXFMT,
|
|
(unsigned long long)(ulong_t)
|
|
tx_fifo_partitions[0],
|
|
(unsigned long long) part0);
|
|
|
|
/*
|
|
* Initialization of Tx_PA_CONFIG register to ignore packet
|
|
* integrity checking.
|
|
*/
|
|
val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
|
|
&bar0->tx_pa_cfg);
|
|
val64 |= XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR |
|
|
XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI |
|
|
XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL |
|
|
XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR;
|
|
xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
|
|
&bar0->tx_pa_cfg);
|
|
|
|
/*
|
|
* Assign MSI-X vectors
|
|
*/
|
|
for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) {
|
|
xge_list_t *item;
|
|
xge_hal_channel_t *channel = NULL;
|
|
|
|
if (!hldev->config.fifo.queue[i].configured ||
|
|
!hldev->config.fifo.queue[i].intr_vector ||
|
|
hldev->config.intr_mode != XGE_HAL_INTR_MODE_MSIX)
|
|
continue;
|
|
|
|
/* find channel */
|
|
xge_list_for_each(item, &hldev->free_channels) {
|
|
xge_hal_channel_t *tmp;
|
|
tmp = xge_container_of(item, xge_hal_channel_t,
|
|
item);
|
|
if (tmp->type == XGE_HAL_CHANNEL_TYPE_FIFO &&
|
|
tmp->post_qid == i) {
|
|
channel = tmp;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (channel) {
|
|
xge_hal_channel_msix_set(channel,
|
|
hldev->config.fifo.queue[i].intr_vector);
|
|
}
|
|
}
|
|
|
|
xge_debug_fifo(XGE_TRACE, "%s", "fifo channels initialized");
|
|
}
|
|
|
|
#ifdef XGE_HAL_ALIGN_XMIT
|
|
void
|
|
__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
|
|
{
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(txdp);
|
|
|
|
if (txdl_priv->align_dma_addr != 0) {
|
|
xge_os_dma_unmap(fifo->channel.pdev,
|
|
txdl_priv->align_dma_handle,
|
|
txdl_priv->align_dma_addr,
|
|
fifo->align_size,
|
|
XGE_OS_DMA_DIR_TODEVICE);
|
|
|
|
txdl_priv->align_dma_addr = 0;
|
|
}
|
|
|
|
if (txdl_priv->align_vaddr != NULL) {
|
|
xge_os_dma_free(fifo->channel.pdev,
|
|
txdl_priv->align_vaddr,
|
|
fifo->align_size,
|
|
&txdl_priv->align_dma_acch,
|
|
&txdl_priv->align_dma_handle);
|
|
|
|
|
|
txdl_priv->align_vaddr = NULL;
|
|
}
|
|
}
|
|
|
|
xge_hal_status_e
|
|
__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
|
|
{
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
|
|
xge_assert(txdp);
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(txdp);
|
|
|
|
/* allocate alignment DMA-buffer */
|
|
txdl_priv->align_vaddr = (char *)xge_os_dma_malloc(fifo->channel.pdev,
|
|
fifo->align_size,
|
|
XGE_OS_DMA_CACHELINE_ALIGNED |
|
|
XGE_OS_DMA_STREAMING,
|
|
&txdl_priv->align_dma_handle,
|
|
&txdl_priv->align_dma_acch);
|
|
if (txdl_priv->align_vaddr == NULL) {
|
|
return XGE_HAL_ERR_OUT_OF_MEMORY;
|
|
}
|
|
|
|
/* map it */
|
|
txdl_priv->align_dma_addr = xge_os_dma_map(fifo->channel.pdev,
|
|
txdl_priv->align_dma_handle, txdl_priv->align_vaddr,
|
|
fifo->align_size,
|
|
XGE_OS_DMA_DIR_TODEVICE, XGE_OS_DMA_STREAMING);
|
|
|
|
if (txdl_priv->align_dma_addr == XGE_OS_INVALID_DMA_ADDR) {
|
|
__hal_fifo_dtr_align_free_unmap(channelh, dtrh);
|
|
return XGE_HAL_ERR_OUT_OF_MAPPING;
|
|
}
|
|
|
|
return XGE_HAL_OK;
|
|
}
|
|
#endif
|
|
|
|
|