750 lines
18 KiB
Plaintext
750 lines
18 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1043a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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fman0 = &fman0;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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ethernet5 = &enet5;
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ethernet6 = &enet6;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* We expect the enable-method for cpu's to be "psci", but this
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* is dependent on the SoC FW, which will fill this in.
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*
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* Currently supported enable-method is psci v0.2
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*/
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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idle-states {
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/*
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* PSCI node is not added default, U-boot will add missing
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* parts if it determines to use PSCI.
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*/
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entry-method = "psci";
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CPU_PH20: cpu-ph20 {
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compatible = "arm,idle-state";
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idle-state-name = "PH20";
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arm,psci-suspend-param = <0x0>;
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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/* DRAM space 1, size: 2GiB DRAM */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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compatible = "shared-dma-pool";
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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no-map;
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};
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qman_fqd: qman-fqd {
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compatible = "shared-dma-pool";
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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no-map;
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};
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qman_pfdr: qman-pfdr {
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compatible = "shared-dma-pool";
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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no-map;
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};
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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reboot {
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compatible ="syscon-reboot";
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regmap = <&dcfg>;
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offset = <0xb0>;
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mask = <0x02>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 3>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf08>, /* Physical Secure PPI */
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<1 14 0xf08>, /* Physical Non-Secure PPI */
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<1 11 0xf08>, /* Virtual PPI */
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<1 10 0xf08>; /* Hypervisor PPI */
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fsl,erratum-a008585;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 106 0x4>,
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<0 107 0x4>,
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<0 95 0x4>,
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<0 97 0x4>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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gic: interrupt-controller@1400000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1401000 0 0x1000>, /* GICD */
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<0x0 0x1402000 0 0x2000>, /* GICC */
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<0x0 0x1404000 0 0x2000>, /* GICH */
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<0x0 0x1406000 0 0x2000>; /* GICV */
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interrupts = <1 9 0xf08>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clockgen: clocking@1ee1000 {
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compatible = "fsl,ls1043a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1043a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <0 75 0x4>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 71 0x4>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 72 0x4>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 73 0x4>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 74 0x4>;
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};
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1043a-dcfg", "syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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interrupts = <0 43 0x4>;
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};
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qspi: spi@1550000 {
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compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x4000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 99 0x4>;
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clock-names = "qspi_en", "qspi";
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clocks = <&clockgen 4 0>, <&clockgen 4 0>;
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big-endian;
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status = "disabled";
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <0 62 0x4>;
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clock-frequency = <0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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};
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ddr: memory-controller@1080000 {
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compatible = "fsl,qoriq-memory-controller";
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reg = <0x0 0x1080000 0x0 0x1000>;
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interrupts = <0 144 0x4>;
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big-endian;
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};
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tmu: tmu@1f00000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f00000 0x0 0x10000>;
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interrupts = <0 33 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
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fsl,tmu-calibration = <0x00000000 0x00000026
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0x00000001 0x0000002d
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0x00000002 0x00000032
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0x00000003 0x00000039
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0x00000004 0x0000003f
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0x00000005 0x00000046
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0x00000006 0x0000004d
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0x00000007 0x00000054
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0x00000008 0x0000005a
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0x00000009 0x00000061
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0x0000000a 0x0000006a
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0x0000000b 0x00000071
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0x00010000 0x00000025
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0x00010001 0x0000002c
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0x00010002 0x00000035
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0x00010003 0x0000003d
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0x00010004 0x00000045
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0x00010005 0x0000004e
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0x00010006 0x00000057
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0x00010007 0x00000061
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0x00010008 0x0000006b
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0x00010009 0x00000076
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0x00020000 0x00000029
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0x00020001 0x00000033
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0x00020002 0x0000003d
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0x00020003 0x00000049
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0x00020004 0x00000056
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0x00020005 0x00000061
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0x00020006 0x0000006d
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0x00030000 0x00000021
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0x00030001 0x0000002a
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0x00030002 0x0000003c
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0x00030003 0x0000004e>;
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#thermal-sensor-cells = <1>;
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};
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qman: qman@1880000 {
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compatible = "fsl,qman";
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reg = <0x0 0x1880000 0x0 0x10000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&qman_fqd &qman_pfdr>;
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};
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bman: bman@1890000 {
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compatible = "fsl,bman";
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reg = <0x0 0x1890000 0x0 0x10000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&bman_fbpr>;
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};
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bportals: bman-portals@508000000 {
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ranges = <0x0 0x5 0x08000000 0x8000000>;
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};
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qportals: qman-portals@500000000 {
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ranges = <0x0 0x5 0x00000000 0x8000000>;
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};
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dspi0: spi@2100000 {
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compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 64 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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dspi1: spi@2110000 {
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compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 65 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <0 56 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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dmas = <&edma0 1 39>,
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<&edma0 1 38>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <0 57 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <0 58 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c3: i2c@21b0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21b0000 0x0 0x10000>;
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interrupts = <0 59 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0500 0x0 0x100>;
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interrupts = <0 54 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0600 0x0 0x100>;
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interrupts = <0 54 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart2: serial@21d0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0500 0x0 0x100>;
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interrupts = <0 55 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart3: serial@21d0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0600 0x0 0x100>;
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interrupts = <0 55 0x4>;
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clocks = <&clockgen 4 0>;
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};
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gpio1: gpio@2300000 {
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compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 66 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2310000 {
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compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 67 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2320000 {
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compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 68 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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|
};
|
|
|
|
gpio4: gpio@2330000 {
|
|
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
interrupts = <0 134 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
lpuart0: serial@2950000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2950000 0x0 0x1000>;
|
|
interrupts = <0 48 0x4>;
|
|
clocks = <&clockgen 0 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart1: serial@2960000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2960000 0x0 0x1000>;
|
|
interrupts = <0 49 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart2: serial@2970000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2970000 0x0 0x1000>;
|
|
interrupts = <0 50 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart3: serial@2980000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2980000 0x0 0x1000>;
|
|
interrupts = <0 51 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart4: serial@2990000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2990000 0x0 0x1000>;
|
|
interrupts = <0 52 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@29a0000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x29a0000 0x0 0x1000>;
|
|
interrupts = <0 53 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog0: wdog@2ad0000 {
|
|
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
|
|
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
|
interrupts = <0 83 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "wdog";
|
|
big-endian;
|
|
};
|
|
|
|
edma0: edma@2c00000 {
|
|
#dma-cells = <2>;
|
|
compatible = "fsl,vf610-edma";
|
|
reg = <0x0 0x2c00000 0x0 0x10000>,
|
|
<0x0 0x2c10000 0x0 0x10000>,
|
|
<0x0 0x2c20000 0x0 0x10000>;
|
|
interrupts = <0 103 0x4>,
|
|
<0 103 0x4>;
|
|
interrupt-names = "edma-tx", "edma-err";
|
|
dma-channels = <32>;
|
|
big-endian;
|
|
clock-names = "dmamux0", "dmamux1";
|
|
clocks = <&clockgen 4 0>,
|
|
<&clockgen 4 0>;
|
|
};
|
|
|
|
usb0: usb3@2f00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x2f00000 0x0 0x10000>;
|
|
interrupts = <0 60 0x4>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
usb1: usb3@3000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3000000 0x0 0x10000>;
|
|
interrupts = <0 61 0x4>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
usb2: usb3@3100000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <0 63 0x4>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
sata: sata@3200000 {
|
|
compatible = "fsl,ls1043a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000>,
|
|
<0x0 0x20140520 0x0 0x4>;
|
|
reg-names = "ahci", "sata-ecc";
|
|
interrupts = <0 69 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msi1: msi-controller1@1571000 {
|
|
compatible = "fsl,ls1043a-msi";
|
|
reg = <0x0 0x1571000 0x0 0x8>;
|
|
msi-controller;
|
|
interrupts = <0 116 0x4>;
|
|
};
|
|
|
|
msi2: msi-controller2@1572000 {
|
|
compatible = "fsl,ls1043a-msi";
|
|
reg = <0x0 0x1572000 0x0 0x8>;
|
|
msi-controller;
|
|
interrupts = <0 126 0x4>;
|
|
};
|
|
|
|
msi3: msi-controller3@1573000 {
|
|
compatible = "fsl,ls1043a-msi";
|
|
reg = <0x0 0x1573000 0x0 0x8>;
|
|
msi-controller;
|
|
interrupts = <0 160 0x4>;
|
|
};
|
|
|
|
pcie@3400000 {
|
|
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 118 0x4>, /* controller interrupt */
|
|
<0 117 0x4>; /* PME interrupt */
|
|
interrupt-names = "intr", "pme";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
|
<0000 0 0 2 &gic 0 111 0x4>,
|
|
<0000 0 0 3 &gic 0 112 0x4>,
|
|
<0000 0 0 4 &gic 0 113 0x4>;
|
|
};
|
|
|
|
pcie@3500000 {
|
|
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 128 0x4>,
|
|
<0 127 0x4>;
|
|
interrupt-names = "intr", "pme";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-lanes = <2>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
|
<0000 0 0 2 &gic 0 121 0x4>,
|
|
<0000 0 0 3 &gic 0 122 0x4>,
|
|
<0000 0 0 4 &gic 0 123 0x4>;
|
|
};
|
|
|
|
pcie@3600000 {
|
|
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 162 0x4>,
|
|
<0 161 0x4>;
|
|
interrupt-names = "intr", "pme";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-lanes = <2>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
|
<0000 0 0 2 &gic 0 155 0x4>,
|
|
<0000 0 0 3 &gic 0 156 0x4>,
|
|
<0000 0 0 4 &gic 0 157 0x4>;
|
|
};
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
#include "qoriq-qman-portals.dtsi"
|
|
#include "qoriq-bman-portals.dtsi"
|