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freebsd-nq/sys/gnu/dts/arm64/zte/zx296718.dtsi
Emmanuel Vadot c3f6b2cf9f dts: Import DTS for arm64 
- Most of the boards are using U-Boot, u-boot embed a DTB that isn't
compiled with -@ (overlay ready) so we cannot use overlays. We want
overlays, overlays are nice.
 - The DTS life is going to linux, then sometimes it's imported in
U-Boot but it depend on the SoC family, U-Boot doesn't batch import
every DTS like we do. So sometimes to U-Boot DTS are very old. Or when
an interesting patch in commited upstream it is in Linux X+2 (roughly 4
months from now), we then have to wait for U-Boot to catch up, that
give us between 4 and 6 months to have an update.
 - Some boards like the Marvell ones have 3 DTS, the one in the
vendor U-Boot made by Marvell themselves, the one in u-boot mainline
and the one in Linux. I found that the DTS in the Marvell U-Boot have
some problem with FreeBSD (especially the macchiatobin that declare
node with the same address but not the same size, that is not something
that the rman code can handle, it could be modified, I don't know the
code well enough). Also some compatible are used when they shouldn't,
for example they declare the gpio being orion-gpio while this binding
requires interrupts supports, which the node doesn't have.
 - The above situation is mostly the same with RockChip SoCs (possibly
others, those are the only SoCs I work on that have this problem).

 Note that importing the DTS doesn't mean that every board will use
them, I don't intend to copy the DTB to the GENERIC memstick image for
the Overdrive 1000/3000 for example, the ones provided by the firmware
works fine.
 RPI3 will still stay an exception as we use the DTB provided by the
rpi-firmware package, so they come from the rpi foundation linux fork.
2018-08-23 13:21:01 +00:00

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/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>
/ {
compatible = "zte,zx296718";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
gpio0 = &bgpio0;
gpio1 = &bgpio1;
gpio2 = &bgpio2;
gpio3 = &bgpio3;
gpio4 = &bgpio4;
gpio5 = &bgpio5;
gpio6 = &bgpio6;
serial0 = &uart0;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <888000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <898000>;
clock-latency-ns = <500000>;
};
opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
opp-microvolt = <1015000>;
clock-latency-ns = <500000>;
};
};
clk24k: clk-24k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000>;
clock-output-names = "rtcclk";
};
osc32k: clk-osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "osc32k";
};
osc12m: clk-osc12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
clock-output-names = "osc12m";
};
osc24m: clk-osc24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24m";
};
osc25m: clk-osc25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc25m";
};
osc60m: clk-osc60m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "osc60m";
};
osc99m: clk-osc99m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <99000000>;
clock-output-names = "osc99m";
};
osc125m: clk-osc125m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "osc125m";
};
osc198m: clk-osc198m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <198000000>;
clock-output-names = "osc198m";
};
pll_audio: clk-pll-884m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <884000000>;
clock-output-names = "pll_audio";
};
pll_ddr: clk-pll-932m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <932000000>;
clock-output-names = "pll_ddr";
};
pll_hsic: clk-pll-960m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <960000000>;
clock-output-names = "pll_hsic";
};
pll_mac: clk-pll-1000m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "pll_mac";
};
pll_mm0: clk-pll-1188m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1188000000>;
clock-output-names = "pll_mm0";
};
pll_mm1: clk-pll-1296m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1296000000>;
clock-output-names = "pll_mm1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@2a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x02a00000 0x10000>,
<0x02b00000 0xc0000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
irdec: ir-decoder@111000 {
compatible = "zte,zx296718-irdec";
reg = <0x111000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
iocfg: pin-controller@119000 {
compatible = "zte,zx296718-iocfg";
reg = <0x119000 0x1000>;
};
uart0: uart@11f000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x001feffe>;
reg = <0x11f000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "apb_pclk";
status = "disabled";
};
sd0: mmc@1110000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01110000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
status = "disabled";
};
sd1: mmc@1111000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01111000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <167000000>;
clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-sdio-irq;
cap-sd-highspeed;
status = "disabled";
};
dma: dma-controller@1460000 {
compatible = "zte,zx296702-dma";
reg = <0x01460000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "dmaclk";
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <32>;
};
lsp0crm: clock-controller@1420000 {
compatible = "zte,zx296718-lsp0crm";
reg = <0x01420000 0x1000>;
#clock-cells = <1>;
};
bgpio0: gpio@142d000 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d000 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 48 16>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio1: gpio@142d040 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d040 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 16>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio2: gpio@142d080 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d080 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 3
&pmm 3 32 4
&pmm 7 83 9>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio3: gpio@142d0c0 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 92 16>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio4: gpio@142d100 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d100 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 108 12
&pmm 12 121 4>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio5: gpio@142d140 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d140 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 125 16>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio6: gpio@142d180 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d180 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 141 2>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
lsp1crm: clock-controller@1430000 {
compatible = "zte,zx296718-lsp1crm";
reg = <0x01430000 0x1000>;
#clock-cells = <1>;
};
pwm: pwm@1439000 {
compatible = "zte,zx296718-pwm";
reg = <0x1439000 0x1000>;
clocks = <&lsp1crm LSP1_PWM_PCLK>,
<&lsp1crm LSP1_PWM_WCLK>;
clock-names = "pclk", "wclk";
#pwm-cells = <3>;
status = "disabled";
};
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1440000 0x10000>;
dpc: dpc@0 {
compatible = "zte,zx296718-dpc";
reg = <0x0000 0x1000>, <0x1000 0x1000>,
<0x5000 0x1000>, <0x6000 0x1000>,
<0xa000 0x1000>;
reg-names = "osd", "timing_ctrl",
"dtrc", "vou_ctrl",
"otfppu";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
clock-names = "aclk", "ppu_wclk",
"main_wclk", "aux_wclk";
};
vga: vga@8000 {
compatible = "zte,zx296718-vga";
reg = <0x8000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VGA_I2C_WCLK>;
clock-names = "i2c_wclk";
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
status = "disabled";
};
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
clocks = <&topcrm HDMI_OSC_CEC>,
<&topcrm HDMI_OSC_CLK>,
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
#sound-dai-cells = <0>;
status = "disabled";
};
tvenc: tvenc@2000 {
compatible = "zte,zx296718-tvenc";
reg = <0x2000 0x1000>;
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
status = "disabled";
};
};
topcrm: clock-controller@1461000 {
compatible = "zte,zx296718-topcrm";
reg = <0x01461000 0x1000>;
#clock-cells = <1>;
};
pmm: pin-controller@1462000 {
compatible = "zte,zx296718-pmm";
reg = <0x1462000 0x1000>;
zte,auxiliary-controller = <&iocfg>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};
emmc: mmc@1470000{
compatible = "zte,zx296718-dw-mshc";
reg = <0x01470000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
zte,aon-syscon = <&aon_sysctrl>;
bus-width = <8>;
fifo-depth = <128>;
data-addr = <0x200>;
fifo-watermark-aligned;
clock-frequency = <167000000>;
clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
status = "disabled";
};
audiocrm: clock-controller@1480000 {
compatible = "zte,zx296718-audiocrm";
reg = <0x01480000 0x1000>;
#clock-cells = <1>;
};
i2s0: i2s@1482000 {
compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x01482000 0x1000>;
clocks = <&audiocrm AUDIO_I2S0_WCLK>,
<&audiocrm AUDIO_I2S0_PCLK>;
clock-names = "wclk", "pclk";
assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
assigned-clock-parents = <&topcrm AUDIO_99M>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 22>, <&dma 23>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2c0: i2c@1486000 {
compatible = "zte,zx296718-i2c";
reg = <0x01486000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&audiocrm AUDIO_I2C0_WCLK>;
clock-frequency = <1600000>;
status = "disabled";
aud96p22: codec@22 {
compatible = "zte,zx-aud96p22";
#sound-dai-cells = <0>;
reg = <0x22>;
};
};
spdif0: spdif@1488000 {
compatible = "zte,zx296702-spdif";
reg = <0x1488000 0x1000>;
clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
clock-names = "tx";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#sound-dai-cells = <0>;
dmas = <&dma 30>;
dma-names = "tx";
status = "disabled";
};
};
};
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