920ba15bf9
MFC after: 1 month
430 lines
10 KiB
C
430 lines
10 KiB
C
/*
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* Structure definitions for HVM state that is held by Xen and must
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* be saved along with the domain's memory and device-model state.
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*
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* Copyright (c) 2007 XenSource Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
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#define __XEN_PUBLIC_HVM_SAVE_X86_H__
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/*
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* Save/restore header: general info about the save file.
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*/
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#define HVM_FILE_MAGIC 0x54381286
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#define HVM_FILE_VERSION 0x00000001
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struct hvm_save_header {
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uint32_t magic; /* Must be HVM_FILE_MAGIC */
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uint32_t version; /* File format version */
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uint64_t changeset; /* Version of Xen that saved this file */
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uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
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uint32_t pad0;
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};
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DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
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/*
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* Processor
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*/
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struct hvm_hw_cpu {
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uint8_t fpu_regs[512];
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uint64_t rax;
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uint64_t rbx;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t rsp;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t rip;
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uint64_t rflags;
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uint64_t cr0;
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uint64_t cr2;
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uint64_t cr3;
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uint64_t cr4;
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uint64_t dr0;
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uint64_t dr1;
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uint64_t dr2;
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uint64_t dr3;
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uint64_t dr6;
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uint64_t dr7;
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uint32_t cs_sel;
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uint32_t ds_sel;
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uint32_t es_sel;
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uint32_t fs_sel;
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uint32_t gs_sel;
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uint32_t ss_sel;
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uint32_t tr_sel;
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uint32_t ldtr_sel;
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uint32_t cs_limit;
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uint32_t ds_limit;
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uint32_t es_limit;
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uint32_t fs_limit;
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uint32_t gs_limit;
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uint32_t ss_limit;
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uint32_t tr_limit;
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uint32_t ldtr_limit;
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uint32_t idtr_limit;
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uint32_t gdtr_limit;
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uint64_t cs_base;
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uint64_t ds_base;
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uint64_t es_base;
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uint64_t fs_base;
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uint64_t gs_base;
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uint64_t ss_base;
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uint64_t tr_base;
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uint64_t ldtr_base;
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uint64_t idtr_base;
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uint64_t gdtr_base;
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uint32_t cs_arbytes;
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uint32_t ds_arbytes;
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uint32_t es_arbytes;
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uint32_t fs_arbytes;
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uint32_t gs_arbytes;
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uint32_t ss_arbytes;
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uint32_t tr_arbytes;
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uint32_t ldtr_arbytes;
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uint32_t sysenter_cs;
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uint32_t padding0;
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uint64_t sysenter_esp;
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uint64_t sysenter_eip;
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/* msr for em64t */
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uint64_t shadow_gs;
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/* msr content saved/restored. */
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uint64_t msr_flags;
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uint64_t msr_lstar;
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uint64_t msr_star;
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uint64_t msr_cstar;
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uint64_t msr_syscall_mask;
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uint64_t msr_efer;
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/* guest's idea of what rdtsc() would return */
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uint64_t tsc;
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/* pending event, if any */
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union {
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uint32_t pending_event;
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struct {
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uint8_t pending_vector:8;
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uint8_t pending_type:3;
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uint8_t pending_error_valid:1;
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uint32_t pending_reserved:19;
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uint8_t pending_valid:1;
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};
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};
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/* error code for pending event */
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uint32_t error_code;
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};
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DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
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/*
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* PIC
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*/
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struct hvm_hw_vpic {
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/* IR line bitmasks. */
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uint8_t irr;
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uint8_t imr;
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uint8_t isr;
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/* Line IRx maps to IRQ irq_base+x */
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uint8_t irq_base;
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/*
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* Where are we in ICW2-4 initialisation (0 means no init in progress)?
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* Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
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* Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
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* Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
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*/
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uint8_t init_state:4;
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/* IR line with highest priority. */
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uint8_t priority_add:4;
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/* Reads from A=0 obtain ISR or IRR? */
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uint8_t readsel_isr:1;
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/* Reads perform a polling read? */
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uint8_t poll:1;
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/* Automatically clear IRQs from the ISR during INTA? */
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uint8_t auto_eoi:1;
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/* Automatically rotate IRQ priorities during AEOI? */
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uint8_t rotate_on_auto_eoi:1;
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/* Exclude slave inputs when considering in-service IRQs? */
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uint8_t special_fully_nested_mode:1;
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/* Special mask mode excludes masked IRs from AEOI and priority checks. */
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uint8_t special_mask_mode:1;
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/* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
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uint8_t is_master:1;
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/* Edge/trigger selection. */
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uint8_t elcr;
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/* Virtual INT output. */
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uint8_t int_output;
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};
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DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
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/*
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* IO-APIC
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*/
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#ifdef __ia64__
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#define VIOAPIC_IS_IOSAPIC 1
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#define VIOAPIC_NUM_PINS 24
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#else
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#define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
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#endif
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struct hvm_hw_vioapic {
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uint64_t base_address;
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uint32_t ioregsel;
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uint32_t id;
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union vioapic_redir_entry
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{
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uint64_t bits;
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struct {
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uint8_t vector;
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uint8_t delivery_mode:3;
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uint8_t dest_mode:1;
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uint8_t delivery_status:1;
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uint8_t polarity:1;
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uint8_t remote_irr:1;
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uint8_t trig_mode:1;
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uint8_t mask:1;
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uint8_t reserve:7;
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#if !VIOAPIC_IS_IOSAPIC
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uint8_t reserved[4];
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uint8_t dest_id;
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#else
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uint8_t reserved[3];
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uint16_t dest_id;
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#endif
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} fields;
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} redirtbl[VIOAPIC_NUM_PINS];
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};
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DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
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/*
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* LAPIC
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*/
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struct hvm_hw_lapic {
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uint64_t apic_base_msr;
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uint32_t disabled; /* VLAPIC_xx_DISABLED */
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uint32_t timer_divisor;
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};
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DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
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struct hvm_hw_lapic_regs {
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uint8_t data[1024];
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};
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DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
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/*
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* IRQs
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*/
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struct hvm_hw_pci_irqs {
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/*
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* Virtual interrupt wires for a single PCI bus.
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* Indexed by: device*4 + INTx#.
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*/
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union {
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DECLARE_BITMAP(i, 32*4);
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uint64_t pad[2];
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};
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};
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DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
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struct hvm_hw_isa_irqs {
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/*
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* Virtual interrupt wires for ISA devices.
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* Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
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*/
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union {
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DECLARE_BITMAP(i, 16);
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uint64_t pad[1];
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};
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};
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DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
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struct hvm_hw_pci_link {
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/*
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* PCI-ISA interrupt router.
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* Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
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* the traditional 'barber's pole' mapping ((device + INTx#) & 3).
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* The router provides a programmable mapping from each link to a GSI.
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*/
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uint8_t route[4];
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uint8_t pad0[4];
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};
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DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
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/*
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* PIT
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*/
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struct hvm_hw_pit {
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struct hvm_hw_pit_channel {
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uint32_t count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t status;
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uint8_t read_state;
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uint8_t write_state;
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uint8_t write_latch;
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uint8_t rw_mode;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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} channels[3]; /* 3 x 16 bytes */
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uint32_t speaker_data_on;
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uint32_t pad0;
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};
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DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
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/*
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* RTC
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*/
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#define RTC_CMOS_SIZE 14
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struct hvm_hw_rtc {
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/* CMOS bytes */
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uint8_t cmos_data[RTC_CMOS_SIZE];
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/* Index register for 2-part operations */
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uint8_t cmos_index;
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uint8_t pad0;
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};
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DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
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/*
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* HPET
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*/
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#define HPET_TIMER_NUM 3 /* 3 timers supported now */
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struct hvm_hw_hpet {
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t res0; /* reserved */
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uint64_t config; /* configuration */
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uint64_t res1; /* reserved */
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uint64_t isr; /* interrupt status reg */
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uint64_t res2[25]; /* reserved */
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uint64_t mc64; /* main counter */
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uint64_t res3; /* reserved */
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struct { /* timers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route, not supported now */
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uint64_t res4; /* reserved */
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} timers[HPET_TIMER_NUM];
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uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
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/* Hidden register state */
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uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
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};
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DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
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/*
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* PM timer
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*/
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struct hvm_hw_pmtimer {
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uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
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uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
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uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
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};
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DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
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/*
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* MTRR MSRs
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*/
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struct hvm_hw_mtrr {
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#define MTRR_VCNT 8
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#define NUM_FIXED_MSR 11
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uint64_t msr_pat_cr;
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/* mtrr physbase & physmask msr pair*/
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uint64_t msr_mtrr_var[MTRR_VCNT*2];
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uint64_t msr_mtrr_fixed[NUM_FIXED_MSR];
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uint64_t msr_mtrr_cap;
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uint64_t msr_mtrr_def_type;
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};
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DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr);
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/*
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* Largest type-code in use
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*/
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#define HVM_SAVE_CODE_MAX 14
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#endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */
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