73450c4a7a
The cp110 clock controller controls the clocks and gate of the CP110
hardware block.
Every clock/gate are implemented except the NAND clock.
Sponsored by: Rubicon Communications, LLC ("Netgate")
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MV_CP110_SYSCON_H_
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#define _MV_CP110_SYSCON_H_
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enum mv_cp110_clk_id {
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CP110_PLL_0 = 0,
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CP110_PPV2_CORE,
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CP110_X2CORE,
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CP110_CORE,
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CP110_NAND,
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CP110_SDIO,
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CP110_MAX_CLOCK
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};
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/* Gates */
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#define CP110_CLOCK_GATING_OFFSET 0x220
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struct cp110_gate {
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const char *name;
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uint32_t shift;
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};
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#define CCU_GATE(idx, clkname, s) \
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[idx] = { \
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.name = clkname, \
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.shift = s, \
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},
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#define CP110_GATE_AUDIO 0
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#define CP110_GATE_COMM_UNIT 1
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#define CP110_GATE_NAND 2
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#define CP110_GATE_PPV2 3
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#define CP110_GATE_SDIO 4
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#define CP110_GATE_MG 5
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#define CP110_GATE_MG_CORE 6
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#define CP110_GATE_XOR1 7
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#define CP110_GATE_XOR0 8
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#define CP110_GATE_GOP_DP 9
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#define CP110_GATE_PCIE_X1_0 11
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#define CP110_GATE_PCIE_X1_1 12
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#define CP110_GATE_PCIE_X4 13
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#define CP110_GATE_PCIE_XOR 14
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#define CP110_GATE_SATA 15
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#define CP110_GATE_SATA_USB 16
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#define CP110_GATE_MAIN 17
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#define CP110_GATE_SDMMC_GOP 18
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#define CP110_GATE_SLOW_IO 21
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#define CP110_GATE_USB3H0 22
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#define CP110_GATE_USB3H1 23
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#define CP110_GATE_USB3DEV 24
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#define CP110_GATE_EIP150 25
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#define CP110_GATE_EIP197 26
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#endif
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