f1b665c8fe
- It actually works this time, honest!
- Fine grained TLB shootdowns for SMP on i386. IPI's are very expensive,
so try and optimize things where possible.
- Introduce ranged shootdowns that can be done as a single IPI.
- PG_G support for i386
- Specific-cpu targeted shootdowns. For example, there is no sense in
globally purging the TLB cache for where we are stealing a page from
the local unshared process on the local cpu. Use pm_active to track
this.
- Add some instrumentation for the tlb shootdown code.
- Rip out SMP code from <machine/cpufunc.h>
- Try and fix some very bogus PG_G and PG_PS interactions that were bad
enough to cause vm86 bios calls to break. vm86 depended on our existing
bugs and this was the cause of the VESA panics last time.
- Fix the silly one-line error that caused the 'panic: bad pte' last time.
- Fix a couple of other silly one-line errors that should have caused more
pain than they did.
Some more work is needed:
- pmap_{zero,copy}_page[_idle]. These can be done without IPI's if we
have a hook in cpu_switch.
- The IPI handlers need some cleanup. I have a bogus %ds load that can
be avoided.
- APTD handling is rather bogus and appears to be a large source of
global TLB IPI shootdowns for no really good reason.
I see speedups of between 1.5% and ~4% on buildworlds in a while 1 loop.
I expect to see a bigger difference when there is significant pageout
activity or the system otherwise has memory shortages.
I have backed out a few optimizations that I had been using over the last
few days in order to be a little more conservative. I'll revisit these
again over the next few days as the dust settles.
New option: DISABLE_PG_G - In case I missed something.
655 lines
15 KiB
ArmAsm
655 lines
15 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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#include <machine/apic.h>
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#include <machine/smp.h>
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/* convert an absolute IRQ# into a bitmask */
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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/* make an index into the IO APIC from the IRQ# */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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/*
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*
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; /* 8 ints */ \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define PUSH_DUMMY \
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pushfl ; /* eflags */ \
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pushl %cs ; /* cs */ \
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pushl 12(%esp) ; /* original caller eip */ \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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subl $11*4,%esp ;
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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#define POP_DUMMY \
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addl $16*4,%esp
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#define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
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#define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
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#define MASK_IRQ(irq_num) \
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ICU_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), apic_imen ; \
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jne 7f ; /* masked, don't mask */ \
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orl $IRQ_BIT(irq_num), apic_imen ; /* set the mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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orl $IOART_INTMASK, %eax ; /* set the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already masked */ \
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ICU_UNLOCK
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs must still be masked as we don't clear the source,
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* and the EOI cycle would cause redundant INTs to occur.
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*/
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#define MASK_LEVEL_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), apic_pin_trigger ; \
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jz 9f ; /* edge, don't mask */ \
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MASK_IRQ(irq_num) ; \
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9:
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#ifdef APIC_INTR_REORDER
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#define EOI_IRQ(irq_num) \
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movl apic_isrbit_location + 8 * (irq_num), %eax ; \
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movl (%eax), %eax ; \
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testl apic_isrbit_location + 4 + 8 * (irq_num), %eax ; \
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jz 9f ; /* not active */ \
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movl $0, lapic+LA_EOI ; \
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9:
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#else
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#define EOI_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), lapic+LA_ISR1; \
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jz 9f ; /* not active */ \
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movl $0, lapic+LA_EOI; \
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9:
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#endif
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/*
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* Test to see if the source is currently masked, clear if so.
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*/
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#define UNMASK_IRQ(irq_num) \
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ICU_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), apic_imen ; \
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je 7f ; /* bit clear, not masked */ \
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andl $~IRQ_BIT(irq_num), apic_imen ;/* clear mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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andl $~IOART_INTMASK, %eax ; /* clear the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already unmasked */ \
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ICU_UNLOCK
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs have to be unmasked.
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*/
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#define UNMASK_LEVEL_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), apic_pin_trigger ; \
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jz 9f ; /* edge, don't unmask */ \
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UNMASK_IRQ(irq_num) ; \
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9:
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/*
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* Macros for interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL,%eax ; \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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movl $KPSEL,%eax ; \
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mov %ax,%fs ; \
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FAKE_MCOUNT(13*4(%esp)) ; \
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movl PCPU(CURTHREAD),%ebx ; \
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cmpl $0,TD_CRITNEST(%ebx) ; \
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je 1f ; \
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; \
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movl $1,PCPU(INT_PENDING) ; \
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orl $IRQ_BIT(irq_num),PCPU(FPENDING) ; \
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MASK_LEVEL_IRQ(irq_num) ; \
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movl $0, lapic+LA_EOI ; \
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jmp 10f ; \
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1: ; \
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incl TD_CRITNEST(%ebx) ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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movl $0, lapic+LA_EOI ; \
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lock ; \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4, %eax ; \
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lock ; \
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incl (%eax) ; \
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decl TD_CRITNEST(%ebx) ; \
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cmpl $0,PCPU(INT_PENDING) ; \
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je 2f ; \
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; \
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call i386_unpend ; \
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2: ; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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10: ; \
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MEXITCOUNT ; \
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jmp doreti
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/*
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* Restart a fast interrupt that was held up by a critical section.
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* This routine is called from unpend(). unpend() ensures we are
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* in a critical section and deals with the interrupt nesting level
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* for us. If we previously masked the irq, we have to unmask it.
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*
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* We have a choice. We can regenerate the irq using the 'int'
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* instruction or we can create a dummy frame and call the interrupt
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* handler directly. I've chosen to use the dummy-frame method.
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*/
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#define FAST_UNPEND(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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; \
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pushl %ebp ; \
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movl %esp, %ebp ; \
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PUSH_DUMMY ; \
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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lock ; \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4, %eax ; \
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lock ; \
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incl (%eax) ; \
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UNMASK_LEVEL_IRQ(irq_num) ; \
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POP_DUMMY ; \
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popl %ebp ; \
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ret ; \
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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/* _XintrNN: entry point used by IDT/HWIs via _vec[]. */ \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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mov %ax, %ds ; \
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mov %ax, %es ; \
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movl $KPSEL, %eax ; \
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mov %ax, %fs ; \
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; \
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maybe_extra_ipending ; \
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; \
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MASK_LEVEL_IRQ(irq_num) ; \
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EOI_IRQ(irq_num) ; \
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; \
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movl PCPU(CURTHREAD),%ebx ; \
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cmpl $0,TD_CRITNEST(%ebx) ; \
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je 1f ; \
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movl $1,PCPU(INT_PENDING) ; \
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orl $IRQ_BIT(irq_num),PCPU(IPENDING) ; \
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jmp 10f ; \
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1: ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
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cmpl $0,PCPU(INT_PENDING) ; \
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je 9f ; \
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call i386_unpend ; \
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9: ; \
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pushl $irq_num; /* pass the IRQ */ \
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call sched_ithd ; \
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addl $4, %esp ; /* discard the parameter */ \
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; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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10: ; \
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MEXITCOUNT ; \
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jmp doreti
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xspuriousint
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Xspuriousint:
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/* No EOI cycle used here */
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iret
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/*
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* Global address space TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xinvltlb
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Xinvltlb:
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pushl %eax
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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mov %ax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_gbl(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %eax
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iret
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/*
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* Single page TLB shootdown
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xinvlpg
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Xinvlpg:
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pushl %eax
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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mov %ax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_pg(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl smp_tlb_addr1, %eax
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invlpg (%eax) /* invalidate single page */
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %eax
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iret
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/*
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* Page range TLB shootdown.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xinvlrng
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Xinvlrng:
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pushl %eax
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pushl %edx
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pushl %ds
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movl $KDSEL, %eax /* Kernel data selector */
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mov %ax, %ds
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax /* Private space selector */
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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incl xhits_rng(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl smp_tlb_addr1, %edx
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movl smp_tlb_addr2, %eax
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1: invlpg (%edx) /* invalidate single page */
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addl $PAGE_SIZE, %edx
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cmpl %edx, %eax
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jb 1b
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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lock
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incl smp_tlb_wait
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popl %ds
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popl %edx
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popl %eax
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iret
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/*
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* Forward hardclock to another CPU. Pushes a trapframe and calls
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* forwarded_hardclock().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xhardclock
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Xhardclock:
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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mov %ax, %ds
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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movl PCPU(CURTHREAD),%ebx
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cmpl $0,TD_CRITNEST(%ebx)
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je 1f
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movl $1,PCPU(INT_PENDING)
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orl $1,PCPU(SPENDING);
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jmp 10f
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1:
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incl TD_INTR_NESTING_LEVEL(%ebx)
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call forwarded_hardclock
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decl TD_INTR_NESTING_LEVEL(%ebx)
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10:
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MEXITCOUNT
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jmp doreti
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/*
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* Forward statclock to another CPU. Pushes a trapframe and calls
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* forwarded_statclock().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xstatclock
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Xstatclock:
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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mov %ax, %ds
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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FAKE_MCOUNT(13*4(%esp))
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movl PCPU(CURTHREAD),%ebx
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cmpl $0,TD_CRITNEST(%ebx)
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je 1f
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movl $1,PCPU(INT_PENDING)
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orl $2,PCPU(SPENDING);
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jmp 10f
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1:
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incl TD_INTR_NESTING_LEVEL(%ebx)
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call forwarded_statclock
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decl TD_INTR_NESTING_LEVEL(%ebx)
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10:
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* The other CPU has already executed aston() or need_resched() on our
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* current process, so we simply need to ack the interrupt and return
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* via doreti to run ast().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xcpuast
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Xcpuast:
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PUSH_FRAME
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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FAKE_MCOUNT(13*4(%esp))
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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* - Signals its receipt.
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* - Waits for permission to restart.
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* - Signals its restart.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xcpustop
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Xcpustop:
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pushl %ebp
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movl %esp, %ebp
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ds /* save current data segment */
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pushl %fs
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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movl PCPU(CPUID), %eax
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imull $PCB_SIZE, %eax
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|
leal CNAME(stoppcbs)(%eax), %eax
|
|
pushl %eax
|
|
call CNAME(savectx) /* Save process context */
|
|
addl $4, %esp
|
|
|
|
movl PCPU(CPUID), %eax
|
|
|
|
lock
|
|
btsl %eax, CNAME(stopped_cpus) /* stopped_cpus |= (1<<id) */
|
|
1:
|
|
btl %eax, CNAME(started_cpus) /* while (!(started_cpus & (1<<id))) */
|
|
jnc 1b
|
|
|
|
lock
|
|
btrl %eax, CNAME(started_cpus) /* started_cpus &= ~(1<<id) */
|
|
lock
|
|
btrl %eax, CNAME(stopped_cpus) /* stopped_cpus &= ~(1<<id) */
|
|
|
|
test %eax, %eax
|
|
jnz 2f
|
|
|
|
movl CNAME(cpustop_restartfunc), %eax
|
|
test %eax, %eax
|
|
jz 2f
|
|
movl $0, CNAME(cpustop_restartfunc) /* One-shot */
|
|
|
|
call *%eax
|
|
2:
|
|
popl %fs
|
|
popl %ds /* restore previous data segment */
|
|
popl %edx
|
|
popl %ecx
|
|
popl %eax
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
iret
|
|
|
|
|
|
MCOUNT_LABEL(bintr)
|
|
FAST_INTR(0,fastintr0)
|
|
FAST_INTR(1,fastintr1)
|
|
FAST_INTR(2,fastintr2)
|
|
FAST_INTR(3,fastintr3)
|
|
FAST_INTR(4,fastintr4)
|
|
FAST_INTR(5,fastintr5)
|
|
FAST_INTR(6,fastintr6)
|
|
FAST_INTR(7,fastintr7)
|
|
FAST_INTR(8,fastintr8)
|
|
FAST_INTR(9,fastintr9)
|
|
FAST_INTR(10,fastintr10)
|
|
FAST_INTR(11,fastintr11)
|
|
FAST_INTR(12,fastintr12)
|
|
FAST_INTR(13,fastintr13)
|
|
FAST_INTR(14,fastintr14)
|
|
FAST_INTR(15,fastintr15)
|
|
FAST_INTR(16,fastintr16)
|
|
FAST_INTR(17,fastintr17)
|
|
FAST_INTR(18,fastintr18)
|
|
FAST_INTR(19,fastintr19)
|
|
FAST_INTR(20,fastintr20)
|
|
FAST_INTR(21,fastintr21)
|
|
FAST_INTR(22,fastintr22)
|
|
FAST_INTR(23,fastintr23)
|
|
FAST_INTR(24,fastintr24)
|
|
FAST_INTR(25,fastintr25)
|
|
FAST_INTR(26,fastintr26)
|
|
FAST_INTR(27,fastintr27)
|
|
FAST_INTR(28,fastintr28)
|
|
FAST_INTR(29,fastintr29)
|
|
FAST_INTR(30,fastintr30)
|
|
FAST_INTR(31,fastintr31)
|
|
#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
|
|
/* Threaded interrupts */
|
|
INTR(0,intr0, CLKINTR_PENDING)
|
|
INTR(1,intr1,)
|
|
INTR(2,intr2,)
|
|
INTR(3,intr3,)
|
|
INTR(4,intr4,)
|
|
INTR(5,intr5,)
|
|
INTR(6,intr6,)
|
|
INTR(7,intr7,)
|
|
INTR(8,intr8,)
|
|
INTR(9,intr9,)
|
|
INTR(10,intr10,)
|
|
INTR(11,intr11,)
|
|
INTR(12,intr12,)
|
|
INTR(13,intr13,)
|
|
INTR(14,intr14,)
|
|
INTR(15,intr15,)
|
|
INTR(16,intr16,)
|
|
INTR(17,intr17,)
|
|
INTR(18,intr18,)
|
|
INTR(19,intr19,)
|
|
INTR(20,intr20,)
|
|
INTR(21,intr21,)
|
|
INTR(22,intr22,)
|
|
INTR(23,intr23,)
|
|
INTR(24,intr24,)
|
|
INTR(25,intr25,)
|
|
INTR(26,intr26,)
|
|
INTR(27,intr27,)
|
|
INTR(28,intr28,)
|
|
INTR(29,intr29,)
|
|
INTR(30,intr30,)
|
|
INTR(31,intr31,)
|
|
|
|
FAST_UNPEND(0,fastunpend0)
|
|
FAST_UNPEND(1,fastunpend1)
|
|
FAST_UNPEND(2,fastunpend2)
|
|
FAST_UNPEND(3,fastunpend3)
|
|
FAST_UNPEND(4,fastunpend4)
|
|
FAST_UNPEND(5,fastunpend5)
|
|
FAST_UNPEND(6,fastunpend6)
|
|
FAST_UNPEND(7,fastunpend7)
|
|
FAST_UNPEND(8,fastunpend8)
|
|
FAST_UNPEND(9,fastunpend9)
|
|
FAST_UNPEND(10,fastunpend10)
|
|
FAST_UNPEND(11,fastunpend11)
|
|
FAST_UNPEND(12,fastunpend12)
|
|
FAST_UNPEND(13,fastunpend13)
|
|
FAST_UNPEND(14,fastunpend14)
|
|
FAST_UNPEND(15,fastunpend15)
|
|
FAST_UNPEND(16,fastunpend16)
|
|
FAST_UNPEND(17,fastunpend17)
|
|
FAST_UNPEND(18,fastunpend18)
|
|
FAST_UNPEND(19,fastunpend19)
|
|
FAST_UNPEND(20,fastunpend20)
|
|
FAST_UNPEND(21,fastunpend21)
|
|
FAST_UNPEND(22,fastunpend22)
|
|
FAST_UNPEND(23,fastunpend23)
|
|
FAST_UNPEND(24,fastunpend24)
|
|
FAST_UNPEND(25,fastunpend25)
|
|
FAST_UNPEND(26,fastunpend26)
|
|
FAST_UNPEND(27,fastunpend27)
|
|
FAST_UNPEND(28,fastunpend28)
|
|
FAST_UNPEND(29,fastunpend29)
|
|
FAST_UNPEND(30,fastunpend30)
|
|
FAST_UNPEND(31,fastunpend31)
|
|
MCOUNT_LABEL(eintr)
|
|
|
|
/*
|
|
* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
|
|
*
|
|
* - Calls the generic rendezvous action function.
|
|
*/
|
|
.text
|
|
SUPERALIGN_TEXT
|
|
.globl Xrendezvous
|
|
Xrendezvous:
|
|
PUSH_FRAME
|
|
movl $KDSEL, %eax
|
|
mov %ax, %ds /* use KERNEL data segment */
|
|
mov %ax, %es
|
|
movl $KPSEL, %eax
|
|
mov %ax, %fs
|
|
|
|
call smp_rendezvous_action
|
|
|
|
movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
|
|
POP_FRAME
|
|
iret
|
|
|
|
|
|
.data
|
|
|
|
.globl apic_pin_trigger
|
|
apic_pin_trigger:
|
|
.long 0
|
|
|
|
.text
|