c61b6da840
root nexus device for the CPUs as starting with UltraSPARC IV the 'cpu' nodes hang off of from 'cmp' (chip multi-threading processor) or 'core' or combinations thereof. Also in large UltraSPARC III based machines the 'cpu' nodes hang off of 'ssm' (scalable shared memory) nodes which group snooping-coherency domains together instead of directly from the nexus. It would be great if we could use newbus to deal with the different ways the 'cpu' devices can hang off of pseudo ones but unfortunately both cpu_mp_setmaxid() and sparc64_init() have to work prior to regular device probing. - Add support for UltraSPARC IV and IV+ CPUs. Due to the fact that these are multi-core each CPU has two Fireplane config registers and thus the module/target ID has to be determined differently so the one specific to a certain core is used. Similarly, starting with UltraSPARC IV the individual cores use a different property in the OFW device tree to indicate the CPU/core ID as it no longer is in coincidence with the shared slot/socket ID. This involves changing the MD KTR code to not directly read the UPA module ID either. We use the MID stored in the per-CPU data instead of calling cpu_get_mid() as a replacement in order prevent clobbering any registers as side-effect in the assembler version. This requires CATR() invocations from mp_startup() prior to mapping the per-CPU pages to be removed though. While at it additionally distinguish between CPUs with Fireplane and JBus interconnects as these also use slightly different sizes for the JBus/agent/module/target IDs. - Make sparc64_shutdown_final() static as it's not used outside of machdep.c.
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*-
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* Copyright (c) 1996 Berkeley Software Design, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Berkeley Software Design Inc's name may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from BSDI $Id: ktr.h,v 1.10.2.7 2000/03/16 21:44:42 cp Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_KTR_H_
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#define _MACHINE_KTR_H_
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#include <sys/ktr.h>
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#ifndef LOCORE
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#define KTR_CPU PCPU_GET(mid)
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#else
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#define AND(var, mask, r1, r2) \
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SET(var, r2, r1) ; \
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lduw [r1], r2 ; \
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and r2, mask, r1
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#define TEST(var, mask, r1, r2, l1) \
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AND(var, mask, r1, r2) ; \
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brz r1, l1 ## f ; \
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nop
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/*
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* XXX could really use another register...
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*/
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#define ATR(desc, r1, r2, r3, l1, l2) \
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.sect .rodata ; \
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l1: .asciz desc ; \
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.previous ; \
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SET(ktr_idx, r2, r1) ; \
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lduw [r1], r2 ; \
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l2: add r2, 1, r3 ; \
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set KTR_ENTRIES - 1, r1 ; \
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and r3, r1, r3 ; \
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set ktr_idx, r1 ; \
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casa [r1] ASI_N, r2, r3 ; \
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cmp r2, r3 ; \
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bne %icc, l2 ## b ; \
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mov r3, r2 ; \
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SET(ktr_buf, r3, r1) ; \
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mulx r2, KTR_SIZEOF, r2 ; \
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add r1, r2, r1 ; \
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rd %tick, r2 ; \
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stx r2, [r1 + KTR_TIMESTAMP] ; \
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lduw [PCPU(MID)], r2 ; \
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stw r2, [r1 + KTR_CPU] ; \
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stw %g0, [r1 + KTR_LINE] ; \
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stx %g0, [r1 + KTR_FILE] ; \
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SET(l1 ## b, r3, r2) ; \
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stx r2, [r1 + KTR_DESC]
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#define CATR(mask, desc, r1, r2, r3, l1, l2, l3) \
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set mask, r1 ; \
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TEST(ktr_mask, r1, r2, r2, l3) ; \
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lduw [PCPU(MID)], r1 ; \
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mov 1, r2 ; \
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sllx r2, r1, r1 ; \
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TEST(ktr_cpumask, r1, r2, r3, l3) ; \
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ATR(desc, r1, r2, r3, l1, l2)
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#endif /* LOCORE */
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#endif /* !_MACHINE_KTR_H_ */
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