80d19ff404
always use 'M. Warner Losh' for consistency. 'All Rights Reserved.' was prescribed by the Buenos Aires Copyright Convention of 1910, but has been mostly dead since the early 1990's and completely meaningless since 2000 when Nicaragua ratified the Berne convention. Some files not done due to ambiguity of various types.
89 lines
3.8 KiB
C
89 lines
3.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006 M. Warner Losh.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_TWIREG_H
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#define ARM_AT91_AT91_TWIREG_H
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#define TWI_CR 0x00 /* TWI Control Register */
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#define TWI_MMR 0x04 /* TWI Master Mode Register */
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#define TWI_SMR 0x08 /* TWI Master Mode Register */
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#define TWI_IADR 0x0c /* TWI Internal Address Register */
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#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */
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/* 0x14 reserved */
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/* 0x18 reserved */
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/* 0x1c reserved */
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#define TWI_SR 0x20 /* TWI Status Register */
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#define TWI_IER 0x24 /* TWI Interrupt Enable Register */
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#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */
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#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */
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#define TWI_RHR 0x30 /* TWI Receiver Holding Register */
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#define TWI_THR 0x34 /* TWI Transmit Holding Register */
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/* TWI_CR */
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#define TWI_CR_START (1U << 0) /* Send a start */
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#define TWI_CR_STOP (1U << 1) /* Send a stop */
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#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
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#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
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#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
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#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
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#define TWI_CR_SWRST (1U << 7) /* Software Reset */
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/* TWI_MMR */
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/* TWI_SMR */
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#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
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#define TWI_MMR_MWRITE 0U /* Master Read Direction */
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#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
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#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
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/* TWI_CWGR */
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#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
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#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
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#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
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#define TWI_CWGR_DIV(rate) \
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(at91_is_sam9() || at91_is_sam9xe() ? \
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((at91_master_clock / (4 * (rate))) - 3) : \
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((at91_master_clock / (4 * (rate))) - 2))
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/* TWI_SR */
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/* TWI_IER */
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/* TWI_IDR */
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/* TWI_IMR */
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#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
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#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
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#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
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#define TWI_SR_SVREAD (1U << 3) /* Slave Read */
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#define TWI_SR_SVACC (1U << 4) /* Slave Access */
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#define TWI_SR_GCACC (1U << 5) /* General Call Access */
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#define TWI_SR_OVRE (1U << 6) /* Overrun error */
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#define TWI_SR_UNRE (1U << 7) /* Underrun Error */
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#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
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#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */
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#endif /* ARM_AT91_AT91_TWIREG_H */
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