da089c1410
adapters. Both devices support Gigabit Ethernet and USB 2.0, and the AX88179 supports USB 3.0. The driver was written by kevlo@ and lwhsu@, with a few bug fixes from me. MFC after: 2 months
213 lines
6.9 KiB
C
213 lines
6.9 KiB
C
/*-
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* Copyright (c) 2013 Kevin Lo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define AX88179_PHY_ID 0x03
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#define AXGE_MCAST_FILTER_SIZE 8
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#define AXGE_MAXGE_MCAST 64
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#define AXGE_EEPROM_LEN 0x40
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#define AXGE_RX_CHECKSUM 1
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#define AXGE_TX_CHECKSUM 2
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#define AXGE_ACCESS_MAC 0x01
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#define AXGE_ACCESS_PHY 0x02
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#define AXGE_ACCESS_WAKEUP 0x03
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#define AXGE_ACCESS_EEPROM 0x04
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#define AXGE_ACCESS_EFUSE 0x05
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#define AXGE_RELOAD_EEPROM_EFUSE 0x06
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#define AXGE_WRITE_EFUSE_EN 0x09
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#define AXGE_WRITE_EFUSE_DIS 0x0A
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#define AXGE_ACCESS_MFAB 0x10
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#define AXGE_LINK_STATUS 0x02
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#define AXGE_LINK_STATUS_USB_FS 0x01
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#define AXGE_LINK_STATUS_USB_HS 0x02
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#define AXGE_LINK_STATUS_USB_SS 0x04
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#define AXGE_SROM_ADDR 0x07
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#define AXGE_SROM_DATA_LOW 0x08
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#define AXGE_SROM_DATA_HIGH 0x09
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#define AXGE_SROM_CMD 0x0a
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#define AXGE_SROM_CMD_RD 0x04 /* EEprom read command */
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#define AXGE_SROM_CMD_WR 0x08 /* EEprom write command */
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#define AXGE_SROM_CMD_BUSY 0x10 /* EEprom access module busy */
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#define AXGE_RX_CTL 0x0b
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#define AXGE_RX_CTL_DROPCRCERR 0x0100 /* Drop CRC error packet */
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#define AXGE_RX_CTL_IPE 0x0200 /* 4-byte IP header alignment */
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#define AXGE_RX_CTL_TXPADCRC 0x0400 /* Csum value in rx header 3 */
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#define AXGE_RX_CTL_START 0x0080 /* Ethernet MAC start */
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#define AXGE_RX_CTL_AP 0x0020 /* Accept physical address from
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multicast array */
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#define AXGE_RX_CTL_AM 0x0010
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#define AXGE_RX_CTL_AB 0x0008
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#define AXGE_RX_CTL_HA8B 0x0004
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#define AXGE_RX_CTL_AMALL 0x0002 /* Accept all multicast frames */
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#define AXGE_RX_CTL_PRO 0x0001 /* Promiscuous Mode */
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#define AXGE_RX_CTL_STOP 0x0000 /* Stop MAC */
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#define AXGE_NODE_ID 0x10
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#define AXGE_MULTI_FILTER_ARRY 0x16
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#define AXGE_MEDIUM_STATUS_MODE 0x22
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#define AXGE_MEDIUM_GIGAMODE 0x0001
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#define AXGE_MEDIUM_FULL_DUPLEX 0x0002
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#define AXGE_MEDIUM_ALWAYS_ONE 0x0004
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#define AXGE_MEDIUM_EN_125MHZ 0x0008
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#define AXGE_MEDIUM_RXFLOW_CTRLEN 0x0010
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#define AXGE_MEDIUM_TXFLOW_CTRLEN 0x0020
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#define AXGE_MEDIUM_RECEIVE_EN 0x0100
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#define AXGE_MEDIUM_PS 0x0200
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#define AXGE_MEDIUM_JUMBO_EN 0x8040
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#define AXGE_MONITOR_MODE 0x24
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#define AXGE_MONITOR_MODE_RWLC 0x02
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#define AXGE_MONITOR_MODE_RWMP 0x04
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#define AXGE_MONITOR_MODE_RWWF 0x08
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#define AXGE_MONITOR_MODE_RW_FLAG 0x10
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#define AXGE_MONITOR_MODE_PMEPOL 0x20
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#define AXGE_MONITOR_MODE_PMETYPE 0x40
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#define AXGE_GPIO_CTRL 0x25
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#define AXGE_GPIO_CTRL_GPIO3EN 0x80
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#define AXGE_GPIO_CTRL_GPIO2EN 0x40
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#define AXGE_GPIO_CTRL_GPIO1EN 0x20
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#define AXGE_PHYPWR_RSTCTL 0x26
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#define AXGE_PHYPWR_RSTCTL_BZ 0x0010
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#define AXGE_PHYPWR_RSTCTL_IPRL 0x0020
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#define AXGE_PHYPWR_RSTCTL_AUTODETACH 0x1000
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#define AXGE_RX_BULKIN_QCTRL 0x2e
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#define AXGE_RX_BULKIN_QCTRL_TIME 0x01
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#define AXGE_RX_BULKIN_QCTRL_IFG 0x02
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#define AXGE_RX_BULKIN_QCTRL_SIZE 0x04
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#define AXGE_RX_BULKIN_QTIMR_LOW 0x2f
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#define AXGE_RX_BULKIN_QTIMR_HIGH 0x30
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#define AXGE_RX_BULKIN_QSIZE 0x31
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#define AXGE_RX_BULKIN_QIFG 0x32
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#define AXGE_CLK_SELECT 0x33
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#define AXGE_CLK_SELECT_BCS 0x01
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#define AXGE_CLK_SELECT_ACS 0x02
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#define AXGE_CLK_SELECT_ACSREQ 0x10
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#define AXGE_CLK_SELECT_ULR 0x08
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#define AXGE_RXCOE_CTL 0x34
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#define AXGE_RXCOE_IP 0x01
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#define AXGE_RXCOE_TCP 0x02
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#define AXGE_RXCOE_UDP 0x04
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#define AXGE_RXCOE_ICMP 0x08
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#define AXGE_RXCOE_IGMP 0x10
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#define AXGE_RXCOE_TCPV6 0x20
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#define AXGE_RXCOE_UDPV6 0x40
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#define AXGE_RXCOE_ICMV6 0x80
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#define AXGE_TXCOE_CTL 0x35
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#define AXGE_TXCOE_IP 0x01
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#define AXGE_TXCOE_TCP 0x02
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#define AXGE_TXCOE_UDP 0x04
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#define AXGE_TXCOE_ICMP 0x08
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#define AXGE_TXCOE_IGMP 0x10
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#define AXGE_TXCOE_TCPV6 0x20
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#define AXGE_TXCOE_UDPV6 0x40
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#define AXGE_TXCOE_ICMV6 0x80
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#define AXGE_PAUSE_WATERLVL_HIGH 0x54
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#define AXGE_PAUSE_WATERLVL_LOW 0x55
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#define AXGE_EEP_EFUSE_CORRECT 0x00
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#define AX88179_EEPROM_MAGIC 0x17900b95
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#define AXGE_CONFIG_IDX 0 /* config number 1 */
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#define AXGE_IFACE_IDX 0
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#define AXGE_RXHDR_CRC_ERR 0x80000000
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#define AXGE_RXHDR_L4_ERR (1 << 8)
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#define AXGE_RXHDR_L3_ERR (1 << 9)
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#define AXGE_RXHDR_L4_TYPE_ICMP 2
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#define AXGE_RXHDR_L4_TYPE_IGMP 3
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#define AXGE_RXHDR_L4_TYPE_TCMPV6 5
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#define AXGE_RXHDR_L3_TYPE_IP 1
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#define AXGE_RXHDR_L3_TYPE_IPV6 2
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#define AXGE_RXHDR_L4_TYPE_MASK 0x1c
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#define AXGE_RXHDR_L4_TYPE_UDP 4
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#define AXGE_RXHDR_L4_TYPE_TCP 16
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#define AXGE_RXHDR_L3CSUM_ERR 2
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#define AXGE_RXHDR_L4CSUM_ERR 1
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#define AXGE_RXHDR_CRC_ERR 0x80000000
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#define AXGE_RXHDR_DROP_ERR 0x40000000
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struct axge_csum_hdr {
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uint16_t cstatus;
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#define AXGE_CSUM_HDR_L4_CSUM_ERR 0x0001
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#define AXGE_CSUM_HDR_L3_CSUM_ERR 0x0002
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#define AXGE_CSUM_HDR_L4_TYPE_UDP 0x0004
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#define AXGE_CSUM_HDR_L4_TYPE_ICMP 0x0008
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#define AXGE_CSUM_HDR_L4_TYPE_IGMP 0x000C
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#define AXGE_CSUM_HDR_L4_TYPE_TCP 0x0010
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#define AXGE_CSUM_HDR_L4_TYPE_TCPV6 0x0014
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#define AXGE_CSUM_HDR_L4_TYPE_MASK 0x001C
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#define AXGE_CSUM_HDR_L3_TYPE_IPV4 0x0020
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#define AXGE_CSUM_HDR_L3_TYPE_IPV6 0x0040
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#define AXGE_CSUM_HDR_VLAN_MASK 0x0700
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uint16_t len;
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#define AXGE_CSUM_HDR_LEN_MASK 0x1FFF
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#define AXGE_CSUM_HDR_CRC_ERR 0x2000
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#define AXGE_CSUM_HDR_MII_ERR 0x4000
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#define AXGE_CSUM_HDR_DROP 0x8000
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} __packed;
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#define AXGE_CSUM_RXBYTES(x) ((x) & AXGE_CSUM_HDR_LEN_MASK)
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#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
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/* The interrupt endpoint is currently unused by the ASIX part. */
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enum {
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AXGE_BULK_DT_WR,
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AXGE_BULK_DT_RD,
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AXGE_N_TRANSFER,
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};
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struct axge_softc {
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struct usb_ether sc_ue;
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struct mtx sc_mtx;
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struct usb_xfer *sc_xfer[AXGE_N_TRANSFER];
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int sc_phyno;
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int sc_flags;
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#define AXGE_FLAG_LINK 0x0001 /* got a link */
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};
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#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
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