428 lines
9.7 KiB
C
428 lines
9.7 KiB
C
/*
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* Copyright (c) 2003 Hidetoshi Shimokawa
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* Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the acknowledgement as bellow:
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*
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* This product includes software developed by K. Kobayashi and H. Shimokawa
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*
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _FIREWIRE_H
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#define _FIREWIRE_H 1
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#define DEV_DEF 0
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#define DEV_DV 2
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struct fw_isochreq {
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unsigned char ch:6,
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tag:2;
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};
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struct fw_isobufreq {
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struct fw_bufspec {
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unsigned int nchunk;
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unsigned int npacket;
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unsigned int psize;
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} tx, rx;
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};
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struct fw_addr {
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uint32_t hi;
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uint32_t lo;
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};
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struct fw_asybindreq {
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struct fw_addr start;
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unsigned long len;
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};
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struct fw_reg_req_t {
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uint32_t addr;
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uint32_t data;
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};
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#define MAXREC(x) (2 << (x))
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#define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
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#define FWMAXQUEUE 128
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#define FWLOCALBUS 0xffc0
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#define FWTCODE_WREQQ 0
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#define FWTCODE_WREQB 1
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#define FWTCODE_WRES 2
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#define FWTCODE_RREQQ 4
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#define FWTCODE_RREQB 5
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#define FWTCODE_RRESQ 6
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#define FWTCODE_RRESB 7
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#define FWTCODE_CYCS 8
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#define FWTCODE_LREQ 9
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#define FWTCODE_STREAM 0xa
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#define FWTCODE_LRES 0xb
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#define FWTCODE_PHY 0xe
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#define FWRETRY_1 0
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#define FWRETRY_X 1
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#define FWRETRY_A 2
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#define FWRETRY_B 3
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#define FWRCODE_COMPLETE 0
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#define FWRCODE_ER_CONFL 4
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#define FWRCODE_ER_DATA 5
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#define FWRCODE_ER_TYPE 6
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#define FWRCODE_ER_ADDR 7
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#define FWSPD_S100 0
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#define FWSPD_S200 1
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#define FWSPD_S400 2
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#define FWP_TL_VALID (1 << 7)
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struct fw_isohdr {
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uint32_t hdr[1];
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};
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struct fw_asyhdr {
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uint32_t hdr[4];
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};
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#if BYTE_ORDER == BIG_ENDIAN
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#define BIT4x2(x,y) uint8_t x:4, y:4
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#define BIT16x2(x,y) uint32_t x:16, y:16
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#else
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#define BIT4x2(x,y) uint8_t y:4, x:4
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#define BIT16x2(x,y) uint32_t y:16, x:16
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#endif
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#if BYTE_ORDER == BIG_ENDIAN
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#define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4
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#define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8
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#else
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#define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16
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#define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16
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#endif
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struct fw_pkt {
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union {
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uint32_t ld[0];
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struct {
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COMMON_HDR(, , tcode, );
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} common;
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struct {
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COMMON_HDR(len, chtag, tcode, sy);
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uint32_t payload[0];
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} stream;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, );
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} hdr;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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} rreqq;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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COMMON_RES(src, rtcode, , );
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uint32_t :32;
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} wres;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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BIT16x2(len, extcode);
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} rreqb;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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uint32_t data;
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} wreqq;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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uint32_t data;
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} cyc;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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COMMON_RES(src, rtcode, , );
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uint32_t :32;
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uint32_t data;
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} rresq;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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BIT16x2(len, extcode);
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uint32_t payload[0];
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} wreqb;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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BIT16x2(src, dest_hi);
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uint32_t dest_lo;
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BIT16x2(len, extcode);
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uint32_t payload[0];
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} lreq;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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COMMON_RES(src, rtcode, , );
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uint32_t :32;
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BIT16x2(len, extcode);
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uint32_t payload[0];
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} rresb;
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struct {
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COMMON_HDR(dst, tlrt, tcode, pri);
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COMMON_RES(src, rtcode, , );
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uint32_t :32;
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BIT16x2(len, extcode);
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uint32_t payload[0];
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} lres;
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} mode;
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};
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/*
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* Response code (rtcode)
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*/
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/* The node has successfully completed the command. */
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#define RESP_CMP 0
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/* A resource conflict was detected. The request may be retried. */
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#define RESP_CONFLICT_ERROR 4
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/* Hardware error, data is unavailable. */
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#define RESP_DATA_ERROR 5
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/* A field in the request packet header was set to an unsupported or incorrect
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* value, or an invalid transaction was attempted (e.g., a write to a read-only
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* address). */
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#define RESP_TYPE_ERROR 6
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/* The destination offset field in the request was set to an address not
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* accessible in the destination node. */
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#define RESP_ADDRESS_ERROR 7
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/*
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* Extended transaction code (extcode)
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*/
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#define EXTCODE_MASK_SWAP 1
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#define EXTCODE_CMP_SWAP 2
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#define EXTCODE_FETCH_ADD 3
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#define EXTCODE_LITTLE_ADD 4
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#define EXTCODE_BOUNDED_ADD 5
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#define EXTCODE_WRAP_ADD 6
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struct fw_eui64 {
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uint32_t hi, lo;
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};
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#define FW_EUI64_BYTE(eui, x) \
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((((x)<4)? \
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((eui)->hi >> (8*(3-(x)))): \
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((eui)->lo >> (8*(7-(x)))) \
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) & 0xff)
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#define FW_EUI64_EQUAL(x, y) \
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((x).hi == (y).hi && (x).lo == (y).lo)
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struct fw_asyreq {
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struct fw_asyreq_t{
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unsigned char sped;
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unsigned int type;
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#define FWASREQNODE 0
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#define FWASREQEUI 1
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#define FWASRESTL 2
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#define FWASREQSTREAM 3
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unsigned short len;
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union {
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struct fw_eui64 eui;
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}dst;
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}req;
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struct fw_pkt pkt;
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uint32_t data[512];
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};
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struct fw_devinfo {
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struct fw_eui64 eui;
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uint16_t dst;
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uint16_t status;
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};
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#define FW_MAX_DEVLST 70
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struct fw_devlstreq {
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uint16_t n;
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uint16_t info_len;
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struct fw_devinfo dev[FW_MAX_DEVLST];
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};
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#define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
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#define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
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#define FW_SELF_ID_PORT_NOT_CONNECTED 1
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#define FW_SELF_ID_PORT_NOT_EXISTS 0
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#if BYTE_ORDER == BIG_ENDIAN
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union fw_self_id {
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struct {
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uint32_t id:2,
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phy_id:6,
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sequel:1,
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link_active:1,
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gap_count:6,
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phy_speed:2,
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phy_delay:2,
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contender:1,
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power_class:3,
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port0:2,
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port1:2,
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port2:2,
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initiated_reset:1,
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more_packets:1;
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} p0;
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struct {
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uint32_t
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id:2,
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phy_id:6,
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sequel:1,
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sequence_num:3,
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:2,
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porta:2,
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portb:2,
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portc:2,
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portd:2,
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porte:2,
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portf:2,
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portg:2,
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porth:2,
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:1,
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more_packets:1;
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} p1;
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};
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#else
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union fw_self_id {
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struct {
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uint32_t more_packets:1,
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initiated_reset:1,
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port2:2,
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port1:2,
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port0:2,
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power_class:3,
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contender:1,
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phy_delay:2,
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phy_speed:2,
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gap_count:6,
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link_active:1,
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sequel:1,
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phy_id:6,
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id:2;
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} p0;
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struct {
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uint32_t more_packets:1,
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reserved1:1,
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porth:2,
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portg:2,
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portf:2,
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porte:2,
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portd:2,
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portc:2,
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portb:2,
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porta:2,
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reserved2:2,
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sequence_num:3,
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sequel:1,
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phy_id:6,
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id:2;
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} p1;
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};
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#endif
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struct fw_topology_map {
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uint32_t crc:16,
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crc_len:16;
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uint32_t generation;
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uint32_t self_id_count:16,
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node_count:16;
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union fw_self_id self_id[4*64];
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};
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struct fw_speed_map {
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uint32_t crc:16,
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crc_len:16;
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uint32_t generation;
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uint8_t speed[64][64];
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};
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struct fw_crom_buf {
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struct fw_eui64 eui;
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int len;
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void *ptr;
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};
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/*
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* FireWire specific system requests.
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*/
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#define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq)
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#define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq)
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#define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq)
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#define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq)
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#define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq)
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#define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq)
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#define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq)
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#define FW_IBUSRST _IOR('S', 1, unsigned int)
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#define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq)
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#define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq)
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#define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq)
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#define FW_GTPMAP _IOR('S', 5, struct fw_topology_map)
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#define FW_GCROM _IOWR('S', 7, struct fw_crom_buf)
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#define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
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#define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
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#define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
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#define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
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#define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
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#define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
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#define DUMPDMA _IOWR('S', 82, uint32_t)
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#ifdef _KERNEL
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#define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
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#if defined(__DragonFly__) || __FreeBSD_version < 500000
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#define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8))
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#define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff))
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#endif
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#define MAKEMINOR(f, u, s) \
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unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff))
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#define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
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#define DEV2SUB(x) (dev2unit(x) & 0xff)
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#define FWMEM_FLAG 0x10000
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#define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)
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#endif
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#endif
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