ed510fb04f
latter is a PCIe 10/100 chip. Finally fix the EEPROM reading code so that we can access the EEPROMs on all devices. In order to access the EEPROM, we must select 'EEPROM programming' mode, and then set the EEPROM chip select bit. Previously, we were setting both bits simultaneously, which doesn't work: they must be set in the right sequence. Always obtain the station address from the EEPROM, now that EEPROM reading works correctly. Make the TX interrupt moderation code based on the internal timer optional and turned off by default. Make the re_diag() routine conditional and off by default. When it is on, only use it for the original 8169, which was the only device that that really needed it. Modify interrupt handling to use a fast interrupt handler and fast taskqeueue. Correct the rgephy driver so that it only applies the DSP fixup for PHY revs 0 and 1. Later chips are fixed and don't need the fixup. Make the rgephy driver advertise both 1000_FD and 1000_HD bits in autoneg mode. A couple of the devices don't autoneg correctly unless configured this way.
480 lines
12 KiB
C
480 lines
12 KiB
C
/*-
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* Copyright (c) 2003
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/rgephyreg.h>
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#include "miibus_if.h"
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#include <machine/bus.h>
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#include <pci/if_rlreg.h>
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static int rgephy_probe(device_t);
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static int rgephy_attach(device_t);
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static device_method_t rgephy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, rgephy_probe),
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DEVMETHOD(device_attach, rgephy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t rgephy_devclass;
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static driver_t rgephy_driver = {
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"rgephy",
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rgephy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
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static int rgephy_service(struct mii_softc *, struct mii_data *, int);
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static void rgephy_status(struct mii_softc *);
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static int rgephy_mii_phy_auto(struct mii_softc *);
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static void rgephy_reset(struct mii_softc *);
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static void rgephy_loop(struct mii_softc *);
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static void rgephy_load_dspcode(struct mii_softc *);
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static int rgephy_mii_model;
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static int
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rgephy_probe(device_t dev)
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{
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struct mii_attach_args *ma;
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ma = device_get_ivars(dev);
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
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device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S);
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return(0);
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}
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return(ENXIO);
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}
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static int
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rgephy_attach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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const char *sep = "";
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sc = device_get_softc(dev);
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = rgephy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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#define PRINT(s) printf("%s%s", sep, s); sep = ", "
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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BMCR_ISO);
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#if 0
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP|BMCR_S100);
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#endif
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rgephy_mii_model = MII_MODEL(ma->mii_id2);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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sc->mii_capabilities &= ~BMSR_ANEG;
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device_printf(dev, " ");
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mii_add_media(sc);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
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RGEPHY_BMCR_FDX);
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PRINT(", 1000baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
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PRINT("1000baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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PRINT("auto");
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printf("\n");
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#undef ADD
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#undef PRINT
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rgephy_reset(sc);
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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rgephy_reset(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) rgephy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = RGEPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = RGEPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = RGEPHY_S10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= RGEPHY_BMCR_FDX;
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gig = RGEPHY_1000CTL_AFD;
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} else {
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gig = RGEPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, RGEPHY_MII_BMCR,
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speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
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/*
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* When settning the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE);
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}
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break;
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#ifdef foo
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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#endif
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, RL_GMEDIASTAT);
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if (reg & RL_GMEDIASTAT_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks <= 5/*10*/)
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break;
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sc->mii_ticks = 0;
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rgephy_mii_phy_auto(sc);
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return (0);
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}
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/* Update the media status. */
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rgephy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the RealTek PHYs if the media changes.
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*
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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rgephy_load_dspcode(sc);
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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rgephy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (bmsr & RL_GMEDIASTAT_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
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if (bmcr & RGEPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & RGEPHY_BMCR_AUTOEN) {
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if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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}
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (bmsr & RL_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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else if (bmsr & RL_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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else if (bmsr & RL_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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else
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mii->mii_media_active |= IFM_NONE;
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if (bmsr & RL_GMEDIASTAT_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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}
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static int
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rgephy_mii_phy_auto(struct mii_softc *mii)
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{
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rgephy_loop(mii);
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rgephy_reset(mii);
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PHY_WRITE(mii, RGEPHY_MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL,
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RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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DELAY(100);
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return (EJUSTRETURN);
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}
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static void
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rgephy_loop(struct mii_softc *sc)
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{
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u_int32_t bmsr;
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int i;
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PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
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DELAY(1000);
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for (i = 0; i < 15000; i++) {
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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if (!(bmsr & RGEPHY_BMSR_LINK)) {
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#if 0
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device_printf(sc->mii_dev, "looped %d\n", i);
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#endif
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break;
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}
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DELAY(10);
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}
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}
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#define PHY_SETBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
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#define PHY_CLRBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
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/*
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* Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
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* existing revisions of the 8169S/8110S chips need to be tuned in
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* order to reliably negotiate a 1000Mbps link. This is only needed
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* for rev 0 and rev 1 of the PHY. Later versions work without
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* any fixups.
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*/
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static void
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rgephy_load_dspcode(struct mii_softc *sc)
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{
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int val;
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uint16_t id2;
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id2 = PHY_READ(sc, MII_PHYIDR2);
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if (MII_REV(id2) > 1)
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return;
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PHY_WRITE(sc, 31, 0x0001);
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PHY_WRITE(sc, 21, 0x1000);
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PHY_WRITE(sc, 24, 0x65C7);
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PHY_CLRBIT(sc, 4, 0x0800);
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val = PHY_READ(sc, 4) & 0xFFF;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0x00A1);
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PHY_WRITE(sc, 2, 0x0008);
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PHY_WRITE(sc, 1, 0x1020);
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PHY_WRITE(sc, 0, 0x1000);
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PHY_SETBIT(sc, 4, 0x0800);
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PHY_CLRBIT(sc, 4, 0x0800);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xFF41);
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PHY_WRITE(sc, 2, 0xDE60);
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PHY_WRITE(sc, 1, 0x0140);
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PHY_WRITE(sc, 0, 0x0077);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xDF01);
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PHY_WRITE(sc, 2, 0xDF20);
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PHY_WRITE(sc, 1, 0xFF95);
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PHY_WRITE(sc, 0, 0xFA00);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xFF41);
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PHY_WRITE(sc, 2, 0xDE20);
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PHY_WRITE(sc, 1, 0x0140);
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PHY_WRITE(sc, 0, 0x00BB);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xDF01);
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PHY_WRITE(sc, 2, 0xDF20);
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PHY_WRITE(sc, 1, 0xFF95);
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PHY_WRITE(sc, 0, 0xBF00);
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PHY_SETBIT(sc, 4, 0x0800);
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PHY_CLRBIT(sc, 4, 0x0800);
|
|
PHY_WRITE(sc, 31, 0x0000);
|
|
|
|
DELAY(40);
|
|
}
|
|
|
|
static void
|
|
rgephy_reset(struct mii_softc *sc)
|
|
{
|
|
mii_phy_reset(sc);
|
|
DELAY(1000);
|
|
rgephy_load_dspcode(sc);
|
|
|
|
return;
|
|
}
|