b18bfc3da7
contributions or ideas from Stephen McKay <syssgm@devetir.qld.gov.au>, Alan Cox <alc@cs.rice.edu>, David Greenman <davidg@freebsd.org> and me: More usage of the TAILQ macros. Additional minor fix to queue.h. Performance enhancements to the pageout daemon. Addition of a wait in the case that the pageout daemon has to run immediately. Slightly modify the pageout algorithm. Significant revamp of the pmap/fork code: 1) PTE's and UPAGES's are NO LONGER in the process's map. 2) PTE's and UPAGES's reside in their own objects. 3) TOTAL elimination of recursive page table pagefaults. 4) The page directory now resides in the PTE object. 5) Implemented pmap_copy, thereby speeding up fork time. 6) Changed the pv entries so that the head is a pointer and not an entire entry. 7) Significant cleanup of pmap_protect, and pmap_remove. 8) Removed significant amounts of machine dependent fork code from vm_glue. Pushed much of that code into the machine dependent pmap module. 9) Support more completely the reuse of already zeroed pages (Page table pages and page directories) as being already zeroed. Performance and code cleanups in vm_map: 1) Improved and simplified allocation of map entries. 2) Improved vm_map_copy code. 3) Corrected some minor problems in the simplify code. Implemented splvm (combo of splbio and splimp.) The VM code now seldom uses splhigh. Improved the speed of and simplified kmem_malloc. Minor mod to vm_fault to avoid using pre-zeroed pages in the case of objects with backing objects along with the already existant condition of having a vnode. (If there is a backing object, there will likely be a COW... With a COW, it isn't necessary to start with a pre-zeroed page.) Minor reorg of source to perhaps improve locality of ref.
151 lines
5.6 KiB
C
151 lines
5.6 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: spl.h,v 1.13 1996/02/07 21:52:57 wollman Exp $
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*/
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#ifndef _MACHINE_IPL_H_
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#define _MACHINE_IPL_H_
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#include <machine/ipl.h> /* XXX "machine" means cpu for i386 */
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/*
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* Software interrupt bit numbers in priority order. The priority only
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* determines which swi will be dispatched next; a higher priority swi
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* may be dispatched when a nested h/w interrupt handler returns.
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*/
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#define SWI_TTY (NHWI + 0)
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#define SWI_NET (NHWI + 1)
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#define SWI_CLOCK 30
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#define SWI_AST 31
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/*
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* Corresponding interrupt-pending bits for ipending.
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*/
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#define SWI_TTY_PENDING (1 << SWI_TTY)
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#define SWI_NET_PENDING (1 << SWI_NET)
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#define SWI_CLOCK_PENDING (1 << SWI_CLOCK)
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#define SWI_AST_PENDING (1 << SWI_AST)
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/*
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* Corresponding interrupt-disable masks for cpl. The ordering is now by
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* inclusion (where each mask is considered as a set of bits). Everything
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* except SWI_AST_MASK includes SWI_CLOCK_MASK so that softclock() doesn't
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* run while other swi handlers are running and timeout routines can call
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* swi handlers. Everything includes SWI_AST_MASK so that AST's are masked
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* until just before return to user mode. SWI_TTY_MASK includes SWI_NET_MASK
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* in case tty interrupts are processed at splsofttty() for a tty that is in
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* SLIP or PPP line discipline (this is weaker than merging net_imask with
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* tty_imask in isa.c - splimp() must mask hard and soft tty interrupts, but
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* spltty() apparently only needs to mask soft net interrupts).
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*/
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#define SWI_TTY_MASK (SWI_TTY_PENDING | SWI_CLOCK_MASK | SWI_NET_MASK)
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#define SWI_NET_MASK (SWI_NET_PENDING | SWI_CLOCK_MASK)
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#define SWI_CLOCK_MASK (SWI_CLOCK_PENDING | SWI_AST_MASK)
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#define SWI_AST_MASK SWI_AST_PENDING
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#define SWI_MASK (~HWI_MASK)
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#ifndef LOCORE
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extern unsigned bio_imask; /* group of interrupts masked with splbio() */
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extern unsigned cpl; /* current priority level mask */
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extern volatile unsigned idelayed; /* interrupts to become pending */
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extern volatile unsigned ipending; /* active interrupts masked by cpl */
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extern unsigned net_imask; /* group of interrupts masked with splimp() */
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extern unsigned stat_imask; /* interrupts masked with splstatclock() */
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extern unsigned tty_imask; /* group of interrupts masked with spltty() */
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/*
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* ipending has to be volatile so that it is read every time it is accessed
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* in splx() and spl0(), but we don't want it to be read nonatomically when
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* it is changed. Pretending that ipending is a plain int happens to give
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* suitable atomic code for "ipending |= constant;".
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*/
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#define setdelayed() (*(unsigned *)&ipending |= loadandclear(&idelayed))
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#define setsoftast() (*(unsigned *)&ipending |= SWI_AST_PENDING)
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#define setsoftclock() (*(unsigned *)&ipending |= SWI_CLOCK_PENDING)
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#define setsoftnet() (*(unsigned *)&ipending |= SWI_NET_PENDING)
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#define setsofttty() (*(unsigned *)&ipending |= SWI_TTY_PENDING)
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#define schedsofttty() (*(unsigned *)&idelayed |= SWI_TTY_PENDING)
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#define schedsoftnet() (*(unsigned *)&idelayed |= SWI_NET_PENDING)
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#define softclockpending() (ipending & SWI_CLOCK_PENDING)
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#ifdef __GNUC__
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void splz __P((void));
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#define GENSPL(name, set_cpl) \
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static __inline int name(void) \
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{ \
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unsigned x; \
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\
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__asm __volatile("" : : : "memory"); \
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x = cpl; \
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set_cpl; \
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return (x); \
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}
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GENSPL(splbio, cpl |= bio_imask)
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GENSPL(splclock, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splhigh, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splimp, cpl |= net_imask)
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GENSPL(splnet, cpl |= SWI_NET_MASK)
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GENSPL(splsoftclock, cpl = SWI_CLOCK_MASK)
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GENSPL(splsofttty, cpl |= SWI_TTY_MASK)
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GENSPL(splstatclock, cpl |= stat_imask)
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GENSPL(spltty, cpl |= tty_imask)
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GENSPL(splvm, cpl |= net_imask | bio_imask)
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static __inline void
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spl0(void)
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{
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cpl = SWI_AST_MASK;
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if (ipending & ~SWI_AST_MASK)
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splz();
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}
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static __inline void
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splx(int ipl)
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{
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cpl = ipl;
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if (ipending & ~ipl)
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splz();
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}
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#endif /* __GNUC__ */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_IPL_H_ */
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