e05407d84b
Handles at least Trantor T130 and ProAudioSpectrum adapters. The pas driver has consequently been removed. This driver can be configured without without interrupts. Manpage to follow when PAS16 has been edited in. Reviewed by: phk Submitted by: Serge Vakulenko, <vak@cronyx.ru>
50 lines
2.3 KiB
C
50 lines
2.3 KiB
C
/*
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* Definitions for 53C400 SCSI-controller chip.
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*
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* Derived from Linux NCR-5380 generic driver sources (by Drew Eckhardt).
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*
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* Copyright (C) 1994 Serge Vakulenko (vak@cronyx.ru)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPERS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IC_NCR_53C400_H_
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#define _IC_NCR_53C400_H_
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#define C400_CSR 0 /* rw - Control and Status Reg. */
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#define CSR_5380_ENABLE 0x80
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#define CSR_TRANSFER_DIRECTION 0x40
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#define CSR_TRANSFER_READY_INTR 0x20
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#define CSR_5380_INTR 0x10
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#define CSR_SHARED_INTR 0x08
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#define CSR_HOST_BUF_NOT_READY 0x04 /* read only */
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#define CSR_SCSI_BUF_READY 0x02 /* read only */
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#define CSR_5380_GATED_IRQ 0x01 /* read only */
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#define CSR_BITS "\20\1irq\2sbrdy\3hbrdy\4shintr\5intr\6tintr\7tdir\10enable"
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#define C400_CCR 1 /* rw - Clock Counter Reg. */
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#define C400_HBR 4 /* rw - Host Buffer Reg. */
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#define C400_5380_REG_OFFSET 8 /* Offset of 5380 registers. */
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#endif /* _IC_NCR_53C400_H_ */
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