829 lines
20 KiB
C
829 lines
20 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Samsung Exynos 5 Pad Control
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* Chapter 4, Exynos 5 Dual User's Manual Public Rev 1.00
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include "gpio_if.h"
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#include <arm/samsung/exynos/exynos5_combiner.h>
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#include <arm/samsung/exynos/exynos5_pad.h>
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
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#define MAX_PORTS 5
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#define MAX_NGPIO 253
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#define N_EXT_INTS 16
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#define EXYNOS5250 1
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#define EXYNOS5420 2
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#define PIN_IN 0
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#define PIN_OUT 1
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#define READ4(_sc, _port, _reg) \
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bus_space_read_4(_sc->bst[_port], _sc->bsh[_port], _reg)
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#define WRITE4(_sc, _port, _reg, _val) \
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bus_space_write_4(_sc->bst[_port], _sc->bsh[_port], _reg, _val)
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/*
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* GPIO interface
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*/
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static int pad_pin_max(device_t, int *);
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static int pad_pin_getcaps(device_t, uint32_t, uint32_t *);
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static int pad_pin_getname(device_t, uint32_t, char *);
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static int pad_pin_getflags(device_t, uint32_t, uint32_t *);
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static int pad_pin_setflags(device_t, uint32_t, uint32_t);
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static int pad_pin_set(device_t, uint32_t, unsigned int);
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static int pad_pin_get(device_t, uint32_t, unsigned int *);
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static int pad_pin_toggle(device_t, uint32_t pin);
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struct gpio_bank {
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char *name;
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uint32_t port;
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uint32_t con;
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uint32_t ngpio;
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uint32_t ext_con;
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uint32_t ext_flt_con;
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uint32_t mask;
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uint32_t pend;
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};
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struct pad_softc {
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struct resource *res[MAX_PORTS * 2];
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bus_space_tag_t bst[MAX_PORTS];
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bus_space_handle_t bsh[MAX_PORTS];
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struct mtx sc_mtx;
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int gpio_npins;
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struct gpio_pin gpio_pins[MAX_NGPIO];
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void *gpio_ih[MAX_PORTS];
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device_t dev;
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int model;
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struct resource_spec *pad_spec;
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struct gpio_bank *gpio_map;
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struct interrupt_entry *interrupt_table;
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int nports;
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};
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struct pad_softc *gpio_sc;
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static struct resource_spec pad_spec_5250[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct resource_spec pad_spec_5420[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE },
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{ SYS_RES_MEMORY, 4, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ SYS_RES_IRQ, 4, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{"samsung,exynos5420-padctrl", EXYNOS5420},
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{"samsung,exynos5250-padctrl", EXYNOS5250},
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{NULL, 0}
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};
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struct pad_intr {
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uint32_t enabled;
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void (*ih) (void *);
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void *ih_user;
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};
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static struct pad_intr intr_map[MAX_NGPIO];
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struct interrupt_entry {
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int gpio_number;
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char *combiner_source_name;
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};
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struct interrupt_entry interrupt_table_5250[N_EXT_INTS] = {
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{ 147, "EINT[15]" },
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{ 146, "EINT[14]" },
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{ 145, "EINT[13]" },
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{ 144, "EINT[12]" },
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{ 143, "EINT[11]" },
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{ 142, "EINT[10]" },
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{ 141, "EINT[9]" },
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{ 140, "EINT[8]" },
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{ 139, "EINT[7]" },
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{ 138, "EINT[6]" },
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{ 137, "EINT[5]" },
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{ 136, "EINT[4]" },
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{ 135, "EINT[3]" },
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{ 134, "EINT[2]" },
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{ 133, "EINT[1]" },
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{ 132, "EINT[0]" },
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};
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struct interrupt_entry interrupt_table_5420[N_EXT_INTS] = {
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{ 23, "EINT[15]" },
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{ 22, "EINT[14]" },
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{ 21, "EINT[13]" },
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{ 20, "EINT[12]" },
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{ 19, "EINT[11]" },
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{ 18, "EINT[10]" },
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{ 17, "EINT[9]" },
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{ 16, "EINT[8]" },
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{ 15, "EINT[7]" },
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{ 14, "EINT[6]" },
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{ 13, "EINT[5]" },
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{ 12, "EINT[4]" },
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{ 11, "EINT[3]" },
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{ 10, "EINT[2]" },
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{ 9, "EINT[1]" },
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{ 8, "EINT[0]" },
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};
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/*
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* 253 multi-functional input/output ports
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*/
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static struct gpio_bank gpio_map_5250[] = {
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/* first 132 gpio */
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{ "gpa0", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpa1", 0, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpa2", 0, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpb0", 0, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpb1", 0, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpb2", 0, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 },
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{ "gpb3", 0, 0x0C0, 4, 0x718, 0x830, 0x918, 0xA18 },
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{ "gpc0", 0, 0x0E0, 7, 0x71C, 0x838, 0x91C, 0xA1C },
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{ "gpc1", 0, 0x100, 4, 0x720, 0x840, 0x920, 0xA20 },
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{ "gpc2", 0, 0x120, 7, 0x724, 0x848, 0x924, 0xA24 },
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{ "gpc3", 0, 0x140, 7, 0x728, 0x850, 0x928, 0xA28 },
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{ "gpd0", 0, 0x160, 4, 0x72C, 0x858, 0x92C, 0xA2C },
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{ "gpd1", 0, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 },
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{ "gpy0", 0, 0x1A0, 6, 0, 0, 0, 0 },
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{ "gpy1", 0, 0x1C0, 4, 0, 0, 0, 0 },
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{ "gpy2", 0, 0x1E0, 6, 0, 0, 0, 0 },
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{ "gpy3", 0, 0x200, 8, 0, 0, 0, 0 },
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{ "gpy4", 0, 0x220, 8, 0, 0, 0, 0 },
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{ "gpy5", 0, 0x240, 8, 0, 0, 0, 0 },
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{ "gpy6", 0, 0x260, 8, 0, 0, 0, 0 },
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{ "gpc4", 0, 0x2E0, 7, 0x734, 0x868, 0x934, 0xA34 },
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/* next 32 */
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{ "gpx0", 0, 0xC00, 8, 0xE00, 0xE80, 0xF00, 0xF40 },
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{ "gpx1", 0, 0xC20, 8, 0xE04, 0xE88, 0xF04, 0xF44 },
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{ "gpx2", 0, 0xC40, 8, 0xE08, 0xE90, 0xF08, 0xF48 },
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{ "gpx3", 0, 0xC60, 8, 0xE0C, 0xE98, 0xF0C, 0xF4C },
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{ "gpe0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpe1", 1, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpf0", 1, 0x040, 4, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpf1", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpg0", 1, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpg1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
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{ "gpg2", 1, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 },
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{ "gph0", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
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{ "gph1", 1, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 },
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{ "gpv0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpv1", 2, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpv2", 2, 0x060, 8, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpv3", 2, 0x080, 8, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpv4", 2, 0x0C0, 2, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpz", 3, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 },
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{ NULL, -1, -1, -1, -1, -1, -1, -1 },
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};
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static struct gpio_bank gpio_map_5420[] = {
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/* First 40 */
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{ "gpy7", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpx0", 0, 0xC00, 8, 0x704, 0xE80, 0xF00, 0xF40 },
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{ "gpx1", 0, 0xC20, 8, 0x708, 0xE88, 0xF04, 0xF44 },
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{ "gpx2", 0, 0xC40, 8, 0x70C, 0xE90, 0xF08, 0xF48 },
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{ "gpx3", 0, 0xC60, 8, 0x710, 0xE98, 0xF0C, 0xF4C },
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/* Next 85 */
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{ "gpc0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpc1", 1, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpc2", 1, 0x040, 7, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpc3", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpc4", 1, 0x080, 2, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpd1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
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{ "gpy0", 1, 0x0C0, 6, 0x718, 0x830, 0x918, 0xA18 },
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{ "gpy1", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
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{ "gpy2", 1, 0x100, 6, 0x720, 0x840, 0x920, 0xA20 },
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{ "gpy3", 1, 0x120, 8, 0x724, 0x848, 0x924, 0xA24 },
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{ "gpy4", 1, 0x140, 8, 0x728, 0x850, 0x928, 0xA28 },
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{ "gpy5", 1, 0x160, 8, 0x72C, 0x858, 0x92C, 0xA2C },
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{ "gpy6", 1, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 },
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/* Next 46 */
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{ "gpe0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpe1", 2, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpf0", 2, 0x040, 6, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpf1", 2, 0x060, 8, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpg0", 2, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpg1", 2, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 },
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{ "gpg2", 2, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 },
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{ "gpj4", 2, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C },
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/* Next 54 */
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{ "gpa0", 3, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 },
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{ "gpa1", 3, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 },
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{ "gpa2", 3, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 },
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{ "gpb0", 3, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C },
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{ "gpb1", 3, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 },
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{ "gpb2", 3, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 },
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{ "gpb3", 3, 0x0C0, 8, 0x718, 0x830, 0x918, 0xA18 },
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{ "gpb4", 3, 0x0E0, 2, 0x71C, 0x838, 0x91C, 0xA1C },
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{ "gph0", 3, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 },
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/* Last 7 */
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{ "gpz", 4, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 },
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{ NULL, -1, -1, -1, -1, -1, -1, -1 },
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};
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static int
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get_bank(struct pad_softc *sc, int gpio_number,
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struct gpio_bank *bank, int *pin_shift)
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{
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int ngpio;
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int i;
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int n;
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n = 0;
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for (i = 0; sc->gpio_map[i].ngpio != -1; i++) {
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ngpio = sc->gpio_map[i].ngpio;
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if ((n + ngpio) > gpio_number) {
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*bank = sc->gpio_map[i];
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*pin_shift = (gpio_number - n);
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return (0);
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};
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n += ngpio;
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};
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return (-1);
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}
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static int
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port_intr(void *arg)
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{
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struct port_softc *sc;
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sc = arg;
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return (FILTER_HANDLED);
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}
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static void
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ext_intr(void *arg)
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{
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struct pad_softc *sc;
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void (*ih) (void *);
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void *ih_user;
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int ngpio;
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int found;
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int reg;
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int i,j;
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int n,k;
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sc = arg;
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n = 0;
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for (i = 0; sc->gpio_map[i].ngpio != -1; i++) {
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found = 0;
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ngpio = sc->gpio_map[i].ngpio;
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if (sc->gpio_map[i].pend == 0) {
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n += ngpio;
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continue;
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}
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reg = READ4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend);
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for (j = 0; j < ngpio; j++) {
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if (reg & (1 << j)) {
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found = 1;
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k = (n + j);
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if (intr_map[k].enabled == 1) {
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ih = intr_map[k].ih;
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ih_user = intr_map[k].ih_user;
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ih(ih_user);
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}
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}
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}
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if (found) {
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/* ACK */
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WRITE4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend, reg);
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}
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n += ngpio;
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}
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}
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int
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pad_setup_intr(int gpio_number, void (*ih)(void *), void *ih_user)
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{
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struct interrupt_entry *entry;
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struct pad_intr *pad_irq;
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struct gpio_bank bank;
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struct pad_softc *sc;
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int pin_shift;
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int reg;
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int i;
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sc = gpio_sc;
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if (sc == NULL) {
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device_printf(sc->dev, "Error: pad is not attached\n");
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return (-1);
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}
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if (get_bank(sc, gpio_number, &bank, &pin_shift) != 0)
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return (-1);
|
|
|
|
entry = NULL;
|
|
for (i = 0; i < N_EXT_INTS; i++)
|
|
if (sc->interrupt_table[i].gpio_number == gpio_number)
|
|
entry = &(sc->interrupt_table[i]);
|
|
|
|
if (entry == NULL) {
|
|
device_printf(sc->dev, "Cant find interrupt source for %d\n",
|
|
gpio_number);
|
|
return (-1);
|
|
}
|
|
|
|
#if 0
|
|
printf("Request interrupt name %s\n", entry->combiner_source_name);
|
|
#endif
|
|
|
|
pad_irq = &intr_map[gpio_number];
|
|
pad_irq->enabled = 1;
|
|
pad_irq->ih = ih;
|
|
pad_irq->ih_user = ih_user;
|
|
|
|
/* Setup port as external interrupt source */
|
|
reg = READ4(sc, bank.port, bank.con);
|
|
reg |= (0xf << (pin_shift * 4));
|
|
#if 0
|
|
printf("writing 0x%08x to 0x%08x\n", reg, bank.con);
|
|
#endif
|
|
WRITE4(sc, bank.port, bank.con, reg);
|
|
|
|
/*
|
|
* Configure interrupt pin
|
|
*
|
|
* 0x0 = Sets Low level
|
|
* 0x1 = Sets High level
|
|
* 0x2 = Triggers Falling edge
|
|
* 0x3 = Triggers Rising edge
|
|
* 0x4 = Triggers Both edge
|
|
*
|
|
* TODO: add parameter. For now configure as 0x0
|
|
*/
|
|
reg = READ4(sc, bank.port, bank.ext_con);
|
|
reg &= ~(0x7 << (pin_shift * 4));
|
|
WRITE4(sc, bank.port, bank.ext_con, reg);
|
|
|
|
/* Unmask */
|
|
reg = READ4(sc, bank.port, bank.mask);
|
|
reg &= ~(1 << pin_shift);
|
|
WRITE4(sc, bank.port, bank.mask, reg);
|
|
|
|
combiner_setup_intr(entry->combiner_source_name, ext_intr, sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
device_set_desc(dev, "Exynos Pad Control");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
pad_attach(device_t dev)
|
|
{
|
|
struct gpio_bank bank;
|
|
struct pad_softc *sc;
|
|
int pin_shift;
|
|
int reg;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
|
|
|
|
sc->model = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
|
|
switch (sc->model) {
|
|
case EXYNOS5250:
|
|
sc->pad_spec = pad_spec_5250;
|
|
sc->gpio_map = gpio_map_5250;
|
|
sc->interrupt_table = interrupt_table_5250;
|
|
sc->gpio_npins = 253;
|
|
sc->nports = 4;
|
|
break;
|
|
case EXYNOS5420:
|
|
sc->pad_spec = pad_spec_5420;
|
|
sc->gpio_map = gpio_map_5420;
|
|
sc->interrupt_table = interrupt_table_5420;
|
|
sc->gpio_npins = 232;
|
|
sc->nports = 5;
|
|
break;
|
|
default:
|
|
return (-1);
|
|
};
|
|
|
|
if (bus_alloc_resources(dev, sc->pad_spec, sc->res)) {
|
|
device_printf(dev, "could not allocate resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Memory interface */
|
|
|
|
for (i = 0; i < sc->nports; i++) {
|
|
sc->bst[i] = rman_get_bustag(sc->res[i]);
|
|
sc->bsh[i] = rman_get_bushandle(sc->res[i]);
|
|
};
|
|
|
|
sc->dev = dev;
|
|
|
|
gpio_sc = sc;
|
|
|
|
for (i = 0; i < sc->nports; i++) {
|
|
if ((bus_setup_intr(dev, sc->res[sc->nports + i],
|
|
INTR_TYPE_BIO | INTR_MPSAFE, port_intr,
|
|
NULL, sc, &sc->gpio_ih[i]))) {
|
|
device_printf(dev,
|
|
"ERROR: Unable to register interrupt handler\n");
|
|
return (ENXIO);
|
|
}
|
|
};
|
|
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
sc->gpio_pins[i].gp_pin = i;
|
|
sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
|
|
|
|
if (get_bank(sc, i, &bank, &pin_shift) != 0)
|
|
continue;
|
|
|
|
pin_shift *= 4;
|
|
|
|
reg = READ4(sc, bank.port, bank.con);
|
|
if (reg & (PIN_OUT << pin_shift))
|
|
sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
|
|
else
|
|
sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
|
|
|
|
/* TODO: add other pin statuses */
|
|
|
|
snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
|
|
"pad%d.%d", device_get_unit(dev), i);
|
|
}
|
|
|
|
device_add_child(dev, "gpioc", -1);
|
|
device_add_child(dev, "gpiobus", -1);
|
|
|
|
return (bus_generic_attach(dev));
|
|
}
|
|
|
|
static int
|
|
pad_pin_max(device_t dev, int *maxpin)
|
|
{
|
|
struct pad_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
*maxpin = sc->gpio_npins - 1;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_getname(device_t dev, uint32_t pin, char *name)
|
|
{
|
|
struct pad_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
|
|
{
|
|
struct pad_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
*caps = sc->gpio_pins[i].gp_caps;
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
|
|
{
|
|
struct pad_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
*flags = sc->gpio_pins[i].gp_flags;
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_get(device_t dev, uint32_t pin, unsigned int *val)
|
|
{
|
|
struct gpio_bank bank;
|
|
struct pad_softc *sc;
|
|
int pin_shift;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
if (get_bank(sc, pin, &bank, &pin_shift) != 0)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
if (READ4(sc, bank.port, bank.con + 0x4) & (1 << pin_shift))
|
|
*val = 1;
|
|
else
|
|
*val = 0;
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct gpio_bank bank;
|
|
struct pad_softc *sc;
|
|
int pin_shift;
|
|
int reg;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
if (get_bank(sc, pin, &bank, &pin_shift) != 0)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
reg = READ4(sc, bank.port, bank.con + 0x4);
|
|
if (reg & (1 << pin_shift))
|
|
reg &= ~(1 << pin_shift);
|
|
else
|
|
reg |= (1 << pin_shift);
|
|
WRITE4(sc, bank.port, bank.con + 0x4, reg);
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
static void
|
|
pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin,
|
|
unsigned int flags)
|
|
{
|
|
struct gpio_bank bank;
|
|
int pin_shift;
|
|
int reg;
|
|
|
|
GPIO_LOCK(sc);
|
|
|
|
/*
|
|
* Manage input/output
|
|
*/
|
|
if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
|
|
pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
|
|
|
|
if (get_bank(sc, pin->gp_pin, &bank, &pin_shift) != 0)
|
|
return;
|
|
|
|
pin_shift *= 4;
|
|
|
|
#if 0
|
|
printf("bank is 0x%08x pin_shift %d\n", bank.con, pin_shift);
|
|
#endif
|
|
|
|
if (flags & GPIO_PIN_OUTPUT) {
|
|
pin->gp_flags |= GPIO_PIN_OUTPUT;
|
|
reg = READ4(sc, bank.port, bank.con);
|
|
reg &= ~(0xf << pin_shift);
|
|
reg |= (PIN_OUT << pin_shift);
|
|
WRITE4(sc, bank.port, bank.con, reg);
|
|
} else {
|
|
pin->gp_flags |= GPIO_PIN_INPUT;
|
|
reg = READ4(sc, bank.port, bank.con);
|
|
reg &= ~(0xf << pin_shift);
|
|
WRITE4(sc, bank.port, bank.con, reg);
|
|
}
|
|
}
|
|
|
|
GPIO_UNLOCK(sc);
|
|
}
|
|
|
|
|
|
static int
|
|
pad_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
|
{
|
|
struct pad_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
pad_pin_configure(sc, &sc->gpio_pins[i], flags);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pad_pin_set(device_t dev, uint32_t pin, unsigned int value)
|
|
{
|
|
struct pad_softc *sc;
|
|
struct gpio_bank bank;
|
|
int pin_shift;
|
|
int reg;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
if (sc->gpio_pins[i].gp_pin == pin)
|
|
break;
|
|
}
|
|
|
|
if (i >= sc->gpio_npins)
|
|
return (EINVAL);
|
|
|
|
if (get_bank(sc, pin, &bank, &pin_shift) != 0)
|
|
return (EINVAL);
|
|
|
|
GPIO_LOCK(sc);
|
|
reg = READ4(sc, bank.port, bank.con + 0x4);
|
|
reg &= ~(PIN_OUT << pin_shift);
|
|
if (value)
|
|
reg |= (PIN_OUT << pin_shift);
|
|
WRITE4(sc, bank.port, bank.con + 0x4, reg);
|
|
GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t pad_methods[] = {
|
|
DEVMETHOD(device_probe, pad_probe),
|
|
DEVMETHOD(device_attach, pad_attach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_pin_max, pad_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, pad_pin_getname),
|
|
DEVMETHOD(gpio_pin_getcaps, pad_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_getflags, pad_pin_getflags),
|
|
DEVMETHOD(gpio_pin_get, pad_pin_get),
|
|
DEVMETHOD(gpio_pin_toggle, pad_pin_toggle),
|
|
DEVMETHOD(gpio_pin_setflags, pad_pin_setflags),
|
|
DEVMETHOD(gpio_pin_set, pad_pin_set),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t pad_driver = {
|
|
"gpio",
|
|
pad_methods,
|
|
sizeof(struct pad_softc),
|
|
};
|
|
|
|
static devclass_t pad_devclass;
|
|
|
|
DRIVER_MODULE(pad, simplebus, pad_driver, pad_devclass, 0, 0);
|