b032f27c36
Note this includes changes to all drivers and moves some device firmware loading to use firmware(9) and a separate module (e.g. ral). Also there no longer are separate wlan_scan* modules; this functionality is now bundled into the wlan module. Supported by: Hobnob and Marvell Reviewed by: many Obtained from: Atheros (some bits)
589 lines
19 KiB
C
589 lines
19 KiB
C
/*-
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* Copyright (c) 2007 Marvell Semiconductor, Inc.
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* Copyright (c) 2007 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for the Marvell 88W8335 Wireless LAN controller.
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*/
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#ifndef _DEV_MALO_H
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#define _DEV_MALO_H
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/malo/if_malohal.h>
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#include <dev/malo/if_maloioctl.h>
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#ifndef MALO_TXBUF
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#define MALO_TXBUF 256 /* number of TX descriptors/buffers */
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#endif
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#ifndef MALO_RXBUF
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#define MALO_RXBUF 256 /* number of RX descriptors/buffers */
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#endif
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#define MALO_TXDESC 1 /* max tx descriptors/segments */
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#define MALO_RXSIZE PAGE_SIZE
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#define MALO_RSSI_DUMMY_MARKER 127
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#define MALO_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
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#define MALO_REG_INT_CODE 0x00000C14
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/* From host to ARM */
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#define MALO_REG_H2A_INTERRUPT_EVENTS 0x00000C18
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/* bit definitions for MALO_REG_H2A_INTERRUPT_CAUSE */
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#define MALO_H2ARIC_BIT_PPA_READY 0x00000001
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#define MALO_H2ARIC_BIT_DOOR_BELL 0x00000002 /* bit 1 */
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#define MALO_H2ARIC_BIT_PS 0x00000004
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#define MALO_H2ARIC_BIT_PSPOLL 0x00000008 /* bit 3 */
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/* From ARM to host */
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#define MALO_REG_A2H_INTERRUPT_CAUSE 0x00000C30
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#define MALO_REG_A2H_INTERRUPT_MASK 0x00000C34
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#define MALO_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38
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#define MALO_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C
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/* bit definitions for MALO_REG_A2H_INTERRUPT_CAUSE */
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#define MALO_A2HRIC_BIT_TX_DONE 0x00000001 /* bit 0 */
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#define MALO_A2HRIC_BIT_RX_RDY 0x00000002 /* bit 1 */
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#define MALO_A2HRIC_BIT_OPC_DONE 0x00000004
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#define MALO_A2HRIC_BIT_MAC_EVENT 0x00000008
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#define MALO_A2HRIC_BIT_RX_PROBLEM 0x00000010
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#define MALO_A2HRIC_BIT_RADIO_OFF 0x00000020 /* bit 5 */
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#define MALO_A2HRIC_BIT_RADIO_ON 0x00000040
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#define MALO_A2HRIC_BIT_RADAR_DETECT 0x00000080
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#define MALO_A2HRIC_BIT_ICV_ERROR 0x00000100
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#define MALO_A2HRIC_BIT_MIC_ERROR 0x00000200 /* bit 9 */
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#define MALO_A2HRIC_BIT_QUEUE_EMPTY 0x00000400
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#define MALO_A2HRIC_BIT_QUEUE_FULL 0x00000800
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#define MALO_A2HRIC_BIT_CHAN_SWITCH 0x00001000
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#define MALO_A2HRIC_BIT_TX_WATCHDOG 0x00002000
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#define MALO_A2HRIC_BIT_BA_WATCHDOG 0x00004000
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#define MALO_ISR_SRC_BITS \
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(MALO_A2HRIC_BIT_RX_RDY | \
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MALO_A2HRIC_BIT_TX_DONE | \
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MALO_A2HRIC_BIT_OPC_DONE | \
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MALO_A2HRIC_BIT_MAC_EVENT | \
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MALO_A2HRIC_BIT_MIC_ERROR | \
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MALO_A2HRIC_BIT_ICV_ERROR | \
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MALO_A2HRIC_BIT_RADAR_DETECT | \
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MALO_A2HRIC_BIT_CHAN_SWITCH | \
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MALO_A2HRIC_BIT_TX_WATCHDOG | \
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MALO_A2HRIC_BIT_QUEUE_EMPTY)
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#define MALO_ISR_RESET (1<<15)
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#define MALO_A2HRIC_BIT_MASK MALO_ISR_SRC_BITS
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/* map to 0x80000000 on BAR1 */
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#define MALO_REG_GEN_PTR 0x00000C10
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#define MALO_REG_INT_CODE 0x00000C14
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#define MALO_REG_SCRATCH 0x00000C40
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/*
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* define OpMode for SoftAP/Station mode
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*
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* the following mode signature has to be written to PCI scratch register#0
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* right after successfully downloading the last block of firmware and
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* before waiting for firmware ready signature
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*/
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#define MALO_HOSTCMD_STA_MODE 0x5A
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#define MALO_HOSTCMD_STA_FWRDY_SIGNATURE 0xF0F1F2F4
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/*
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* 16 bit host command code
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*/
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#define MALO_HOSTCMD_NONE 0x0000
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#define MALO_HOSTCMD_CODE_DNLD 0x0001
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#define MALO_HOSTCMD_GET_HW_SPEC 0x0003
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#define MALO_HOSTCMD_SET_HW_SPEC 0x0004
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#define MALO_HOSTCMD_MAC_MULTICAST_ADR 0x0010
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#define MALO_HOSTCMD_SET_WEPKEY 0x0013
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#define MALO_HOSTCMD_802_11_RADIO_CONTROL 0x001c
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#define MALO_HOSTCMD_802_11_RF_TX_POWER 0x001e
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#define MALO_HOSTCMD_802_11_RF_ANTENNA 0x0020
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#define MALO_HOSTCMD_SET_PRE_SCAN 0x0107
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#define MALO_HOSTCMD_SET_POST_SCAN 0x0108
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#define MALO_HOSTCMD_SET_RF_CHANNEL 0x010a
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#define MALO_HOSTCMD_SET_AID 0x010d
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#define MALO_HOSTCMD_SET_RATE 0x0110
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#define MALO_HOSTCMD_SET_SLOT 0x0114
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/* define DFS lab commands */
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#define MALO_HOSTCMD_SET_FIXED_RATE 0x0126
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#define MALO_HOSTCMD_SET_REGION_POWER 0x0128
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#define MALO_HOSTCMD_GET_CALTABLE 0x1134
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/*
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* definition of action or option for each command.
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*/
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/* define general purpose action */
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#define MALO_HOSTCMD_ACT_GEN_GET 0x0000
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#define MALO_HOSTCMD_ACT_GEN_SET 0x0001
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#define MALO_HOSTCMD_ACT_GEN_SET_LIST 0x0002
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/* define action or option for HostCmd_FW_USE_FIXED_RATE */
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#define MALO_HOSTCMD_ACT_USE_FIXED_RATE 0x0001
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#define MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002
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/* INT code register event definition */
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#define MALO_INT_CODE_CMD_FINISHED 0x00000005
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struct malo_cmd_header {
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uint16_t cmd;
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uint16_t length;
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uint16_t seqnum;
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uint16_t result;
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} __packed;
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struct malo_cmd_caltable {
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struct malo_cmd_header cmdhdr;
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uint8_t annex;
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uint8_t index;
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uint8_t len;
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uint8_t reserverd;
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#define MALO_CAL_TBL_SIZE 160
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uint8_t caltbl[MALO_CAL_TBL_SIZE];
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} __packed;
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struct malo_cmd_get_hwspec {
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struct malo_cmd_header cmdhdr;
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u_int8_t version; /* version of the HW */
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u_int8_t hostif; /* host interface */
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/* Max. number of WCB FW can handle */
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u_int16_t num_wcb;
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/* MaxNbr of MC addresses FW can handle */
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u_int16_t num_mcastaddr;
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/* MAC address programmed in HW */
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u_int8_t permaddr[6];
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u_int16_t regioncode;
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/* Number of antenna used */
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u_int16_t num_antenna;
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/* 4 byte of FW release number */
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u_int32_t fw_releasenum;
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u_int32_t wcbbase0;
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u_int32_t rxpdwr_ptr;
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u_int32_t rxpdrd_ptr;
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u_int32_t ul_fw_awakecookie;
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u_int32_t wcbbase1;
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u_int32_t wcbbase2;
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u_int32_t wcbbase3;
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} __packed;
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struct malo_cmd_set_hwspec {
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struct malo_cmd_header cmdhdr;
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uint8_t version; /* HW revision */
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uint8_t hostif; /* Host interface */
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/* Max. number of Multicast address FW can handle */
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uint16_t num_mcastaddr;
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uint8_t permaddr[6]; /* MAC address */
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uint16_t regioncode; /* Region Code */
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/* 4 byte of FW release number */
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uint32_t fwreleasenum;
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/* Firmware awake cookie */
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uint32_t ul_fw_awakecookie;
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/* Device capabilities (see above) */
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uint32_t devicecaps;
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uint32_t rxpdwrptr; /* Rx shared memory queue */
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/* # TX queues in WcbBase array */
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uint32_t num_txqueues;
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/* TX WCB Rings */
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uint32_t wcbbase[MALO_MAX_TXWCB_QUEUES];
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uint32_t flags;
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uint32_t txwcbnum_per_queue;
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uint32_t total_rxwcb;
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} __packed;
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/* DS 802.11 */
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struct malo_cmd_rf_antenna {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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/* Number of antennas or 0xffff (diversity) */
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uint16_t mode;
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} __packed;
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struct malo_cmd_radio_control {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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/*
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* bit 0 : 1 = on, 0 = off
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* bit 1 : 1 = long, 0 = short
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* bit 2 : 1 = auto, 0 = fix
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*/
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uint16_t control;
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uint16_t radio_on;
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} __packed;
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struct malo_cmd_fw_set_wmmmode {
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struct malo_cmd_header cmdhdr;
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uint16_t action; /* 0 -> unset, 1 -> set */
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} __packed;
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struct malo_cmd_fw_set_rf_channel {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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uint8_t cur_channel; /* channel # */
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} __packed;
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#define MALO_TX_POWER_LEVEL_TOTAL 8
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struct malo_cmd_rf_tx_power {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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uint16_t support_txpower_level;
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uint16_t current_txpower_level;
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uint16_t reserved;
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uint16_t power_levellist[MALO_TX_POWER_LEVEL_TOTAL];
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} __packed;
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struct malo_fixrate_flag {
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/* lower rate after the retry count. 0 = legacy, 1 = HT */
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uint32_t type;
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/* 0: retry count is not valid, 1: use retry count specified */
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uint32_t retrycount_valid;
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} __packed;
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struct malo_fixed_rate_entry {
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struct malo_fixrate_flag typeflags;
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/* legacy rate(not index) or an MCS code. */
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uint32_t fixedrate;
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uint32_t retrycount;
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} __packed;
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struct malo_cmd_fw_use_fixed_rate {
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struct malo_cmd_header cmdhdr;
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/*
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* MALO_HOSTCMD_ACT_GEN_GET 0x0000
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* MALO_HOSTCMD_ACT_GEN_SET 0x0001
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* MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002
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*/
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uint32_t action;
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/* use fixed rate specified but firmware can drop to */
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uint32_t allowratedrop;
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uint32_t entrycount;
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struct malo_fixed_rate_entry fixedrate_table[4];
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uint8_t multicast_rate;
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uint8_t multirate_txtype;
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uint8_t management_rate;
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} __packed;
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#define MALO_RATE_INDEX_MAX_ARRAY 14
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struct malo_cmd_fw_set_aid {
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struct malo_cmd_header cmdhdr;
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uint16_t associd;
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uint8_t macaddr[6]; /* AP's Mac Address(BSSID) */
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uint32_t gprotection;
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uint8_t aprates[MALO_RATE_INDEX_MAX_ARRAY];
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} __packed;
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struct malo_cmd_prescan {
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struct malo_cmd_header cmdhdr;
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} __packed;
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struct malo_cmd_postscan {
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struct malo_cmd_header cmdhdr;
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uint32_t isibss;
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uint8_t bssid[6];
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} __packed;
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struct malo_cmd_fw_setslot {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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/* slot = 0 if regular, slot = 1 if short. */
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uint8_t slot;
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};
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struct malo_cmd_set_rate {
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struct malo_cmd_header cmdhdr;
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uint8_t dataratetype;
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uint8_t rateindex;
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uint8_t aprates[14];
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} __packed;
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struct malo_cmd_wepkey {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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uint8_t len;
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uint8_t flags;
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uint16_t index;
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uint8_t value[IEEE80211_KEYBUF_SIZE];
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uint8_t txmickey[IEEE80211_WEP_MICLEN];
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uint8_t rxmickey[IEEE80211_WEP_MICLEN];
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uint64_t rxseqctr;
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uint64_t txseqctr;
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} __packed;
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struct malo_cmd_mcast {
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struct malo_cmd_header cmdhdr;
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uint16_t action;
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uint16_t numaddr;
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#define MALO_HAL_MCAST_MAX 32
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uint8_t maclist[6*32];
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} __packed;
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/*
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* DMA state for tx/rx descriptors.
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*/
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/*
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* Common "base class" for tx/rx descriptor resources
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* allocated using the bus dma api.
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*/
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struct malo_descdma {
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const char* dd_name;
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void *dd_desc; /* descriptors */
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bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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bus_size_t dd_desc_len; /* size of dd_desc */
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bus_dma_segment_t dd_dseg;
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int dd_dnseg; /* number of segments */
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bus_dma_tag_t dd_dmat; /* bus DMA tag */
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bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
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void *dd_bufptr; /* associated buffers */
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};
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/*
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* Hardware tx/rx descriptors.
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*
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* NB: tx descriptor size must match f/w expected size
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* because f/w prefetch's the next descriptor linearly
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* and doesn't chase the next pointer.
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*/
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struct malo_txdesc {
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uint32_t status;
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#define MALO_TXD_STATUS_IDLE 0x00000000
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#define MALO_TXD_STATUS_USED 0x00000001
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#define MALO_TXD_STATUS_OK 0x00000001
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#define MALO_TXD_STATUS_OK_RETRY 0x00000002
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#define MALO_TXD_STATUS_OK_MORE_RETRY 0x00000004
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#define MALO_TXD_STATUS_MULTICAST_TX 0x00000008
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#define MALO_TXD_STATUS_BROADCAST_TX 0x00000010
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#define MALO_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
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#define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
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#define MALO_TXD_STATUS_FAILED_XRETRY MALO_TXD_STATUS_FAILED_EXCEED_LIMIT
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#define MALO_TXD_STATUS_FAILED_AGING 0x00000080
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#define MALO_TXD_STATUS_FW_OWNED 0x80000000
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uint8_t datarate;
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uint8_t txpriority;
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uint16_t qosctrl;
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uint32_t pktptr;
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uint16_t pktlen;
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uint8_t destaddr[6];
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uint32_t physnext;
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uint32_t sap_pktinfo;
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uint16_t format;
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#define MALO_TXD_FORMAT 0x0001 /* frame format/rate */
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#define MALO_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */
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#define MALO_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */
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#define MALO_TXD_RATE_S 3
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/* NB: 3 is reserved */
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#define MALO_TXD_ANTENNA 0x1800 /* antenna select */
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#define MALO_TXD_ANTENNA_S 11
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uint16_t pad; /* align to 4-byte boundary */
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} __packed;
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#define MALO_TXDESC_SYNC(txq, ds, how) do { \
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bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \
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} while(0)
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struct malo_rxdesc {
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uint8_t rxcontrol; /* control element */
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#define MALO_RXD_CTRL_DRIVER_OWN 0x00
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#define MALO_RXD_CTRL_OS_OWN 0x04
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#define MALO_RXD_CTRL_DMA_OWN 0x80
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uint8_t snr; /* signal to noise ratio */
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uint8_t status; /* status field w/ USED bit */
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#define MALO_RXD_STATUS_IDLE 0x00
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#define MALO_RXD_STATUS_OK 0x01
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#define MALO_RXD_STATUS_MULTICAST_RX 0x02
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#define MALO_RXD_STATUS_BROADCAST_RX 0x04
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#define MALO_RXD_STATUS_FRAGMENT_RX 0x08
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#define MALO_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff
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#define MALO_RXD_STATUS_DECRYPT_ERR_MASK 0x80
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#define MALO_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02
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#define MALO_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04
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#define MALO_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08
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uint8_t channel; /* channel # pkt received on */
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uint16_t pktlen; /* total length of received data */
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uint8_t nf; /* noise floor */
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uint8_t rate; /* received data rate */
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uint32_t physbuffdata; /* physical address of payload data */
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uint32_t physnext; /* physical address of next RX desc */
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uint16_t qosctrl; /* received QosCtrl field variable */
|
|
uint16_t htsig2; /* like name states */
|
|
} __packed;
|
|
|
|
#define MALO_RXDESC_SYNC(sc, ds, how) do { \
|
|
bus_dmamap_sync((sc)->malo_rxdma.dd_dmat, \
|
|
(sc)->malo_rxdma.dd_dmamap, how); \
|
|
} while (0)
|
|
|
|
struct malo_rxbuf {
|
|
STAILQ_ENTRY(malo_rxbuf) bf_list;
|
|
void *bf_desc; /* h/w descriptor */
|
|
bus_addr_t bf_daddr; /* physical addr of desc */
|
|
bus_dmamap_t bf_dmamap;
|
|
bus_addr_t bf_data; /* physical addr of rx data */
|
|
struct mbuf *bf_m; /* jumbo mbuf */
|
|
};
|
|
typedef STAILQ_HEAD(, malo_rxbuf) malo_rxbufhead;
|
|
|
|
/*
|
|
* Software backed version of tx/rx descriptors. We keep
|
|
* the software state out of the h/w descriptor structure
|
|
* so that may be allocated in uncached memory w/o paying
|
|
* performance hit.
|
|
*/
|
|
struct malo_txbuf {
|
|
STAILQ_ENTRY(malo_txbuf) bf_list;
|
|
void *bf_desc; /* h/w descriptor */
|
|
bus_addr_t bf_daddr; /* physical addr of desc */
|
|
bus_dmamap_t bf_dmamap; /* DMA map for descriptors */
|
|
int bf_nseg;
|
|
bus_dma_segment_t bf_segs[MALO_TXDESC];
|
|
struct mbuf *bf_m;
|
|
struct ieee80211_node *bf_node;
|
|
struct malo_txq *bf_txq; /* backpointer to tx q/ring */
|
|
};
|
|
typedef STAILQ_HEAD(, malo_txbuf) malo_txbufhead;
|
|
|
|
/*
|
|
* TX/RX ring definitions. There are 4 tx rings, one
|
|
* per AC, and 1 rx ring. Note carefully that transmit
|
|
* descriptors are treated as a contiguous chunk and the
|
|
* firmware pre-fetches descriptors. This means that we
|
|
* must preserve order when moving descriptors between
|
|
* the active+free lists; otherwise we may stall transmit.
|
|
*/
|
|
struct malo_txq {
|
|
struct malo_descdma dma; /* bus dma resources */
|
|
struct mtx lock; /* tx q lock */
|
|
char name[12]; /* e.g. "malo0_txq4" */
|
|
int qnum; /* f/w q number */
|
|
int txpri; /* f/w tx priority */
|
|
int nfree; /* # buffers on free list */
|
|
malo_txbufhead free; /* queue of free buffers */
|
|
malo_txbufhead active; /* queue of active buffers */
|
|
};
|
|
|
|
#define MALO_TXQ_LOCK_INIT(_sc, _tq) do { \
|
|
snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \
|
|
device_get_nameunit((_sc)->malo_dev), (_tq)->qnum); \
|
|
mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \
|
|
} while (0)
|
|
#define MALO_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock)
|
|
#define MALO_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock)
|
|
#define MALO_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock)
|
|
#define MALO_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED)
|
|
|
|
/*
|
|
* Each packet has fixed front matter: a 2-byte length
|
|
* of the payload, followed by a 4-address 802.11 header
|
|
* (regardless of the actual header and always w/o any
|
|
* QoS header). The payload then follows.
|
|
*/
|
|
struct malo_txrec {
|
|
uint16_t fwlen;
|
|
struct ieee80211_frame_addr4 wh;
|
|
} __packed;
|
|
|
|
struct malo_vap {
|
|
struct ieee80211vap malo_vap;
|
|
int (*malo_newstate)(struct ieee80211vap *,
|
|
enum ieee80211_state, int);
|
|
};
|
|
#define MALO_VAP(vap) ((struct malo_vap *)(vap))
|
|
|
|
struct malo_softc {
|
|
device_t malo_dev;
|
|
struct ifnet *malo_ifp; /* interface common */
|
|
struct mtx malo_mtx; /* master lock (recursive) */
|
|
struct taskqueue *malo_tq; /* private task queue */
|
|
|
|
bus_dma_tag_t malo_dmat; /* bus DMA tag */
|
|
bus_space_handle_t malo_io0h; /* BAR 0 */
|
|
bus_space_tag_t malo_io0t;
|
|
bus_space_handle_t malo_io1h; /* BAR 1 */
|
|
bus_space_tag_t malo_io1t;
|
|
|
|
unsigned int malo_invalid : 1,/* disable hardware accesses */
|
|
malo_recvsetup : 1, /* recv setup */
|
|
malo_fixedrate: 1; /* use fixed tx rate */
|
|
|
|
struct malo_hal *malo_mh; /* h/w access layer */
|
|
struct malo_hal_hwspec malo_hwspecs; /* h/w capabilities */
|
|
struct malo_hal_txrxdma malo_hwdma; /* h/w dma setup */
|
|
uint32_t malo_imask; /* interrupt mask copy */
|
|
struct malo_hal_channel malo_curchan;
|
|
u_int16_t malo_rxantenna; /* rx antenna */
|
|
u_int16_t malo_txantenna; /* tx antenna */
|
|
|
|
struct malo_descdma malo_rxdma; /* rx bus dma resources */
|
|
malo_rxbufhead malo_rxbuf; /* rx buffers */
|
|
struct malo_rxbuf *malo_rxnext; /* next rx buffer to process */
|
|
struct task malo_rxtask; /* rx int processing */
|
|
|
|
struct malo_txq malo_txq[MALO_NUM_TX_QUEUES];
|
|
struct task malo_txtask; /* tx int processing */
|
|
|
|
struct bpf_if *malo_drvbpf;
|
|
struct malo_tx_radiotap_header malo_tx_th;
|
|
int malo_tx_th_len;
|
|
struct malo_rx_radiotap_header malo_rx_th;
|
|
int malo_rx_th_len;
|
|
|
|
struct malo_stats malo_stats; /* interface statistics */
|
|
int malo_debug;
|
|
};
|
|
|
|
#define MALO_LOCK_INIT(_sc) \
|
|
mtx_init(&(_sc)->malo_mtx, device_get_nameunit((_sc)->malo_dev), \
|
|
NULL, MTX_DEF | MTX_RECURSE)
|
|
#define MALO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->malo_mtx)
|
|
#define MALO_LOCK(_sc) mtx_lock(&(_sc)->malo_mtx)
|
|
#define MALO_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_mtx)
|
|
#define MALO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->malo_mtx, MA_OWNED)
|
|
|
|
#define MALO_RXFREE_INIT(_sc) \
|
|
mtx_init(&(_sc)->malo_rxlock, device_get_nameunit((_sc)->malo_dev), \
|
|
NULL, MTX_DEF)
|
|
#define MALO_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->malo_rxlock)
|
|
#define MALO_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->malo_rxlock)
|
|
#define MALO_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_rxlock)
|
|
#define MALO_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->malo_rxlock, \
|
|
MA_OWNED)
|
|
|
|
int malo_attach(uint16_t, struct malo_softc *);
|
|
int malo_intr(void *);
|
|
int malo_detach(struct malo_softc *);
|
|
void malo_shutdown(struct malo_softc *);
|
|
void malo_suspend(struct malo_softc *);
|
|
void malo_resume(struct malo_softc *);
|
|
|
|
#endif
|