be34efe2f3
* add debugging * disable the manual noise floor calibration and tracking done by the HAL; this interferes with the normal calibration path and will lock up the RX side * don't program short report / priority if they're provided as NOVAL.
631 lines
20 KiB
C
631 lines
20 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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//#ifdef AH_SUPPORT_AR9300
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar9300_freebsd_inc.h"
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#include "ar9300/ar9300phy.h"
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300reg.h"
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#include "ar9300/ar9300desc.h"
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#if ATH_SUPPORT_SPECTRAL
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/*
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* Default 9300 spectral scan parameters
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*/
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#define AR9300_SPECTRAL_SCAN_ENA 0
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#define AR9300_SPECTRAL_SCAN_ACTIVE 0
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#define AR9300_SPECTRAL_SCAN_FFT_PERIOD 8
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#define AR9300_SPECTRAL_SCAN_PERIOD 1
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#define AR9300_SPECTRAL_SCAN_COUNT 16 /* used to be 128 */
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#define AR9300_SPECTRAL_SCAN_SHORT_REPEAT 1
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/* constants */
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#define MAX_RADAR_DC_PWR_THRESH 127
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#define MAX_RADAR_RSSI_THRESH 0x3f
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#define MAX_RADAR_HEIGHT 0x3f
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#define MAX_CCA_THRESH 127
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#define ENABLE_ALL_PHYERR 0xffffffff
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void ar9300_disable_cck(struct ath_hal *ah);
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void ar9300_disable_radar(struct ath_hal *ah);
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void ar9300_disable_restart(struct ath_hal *ah);
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void ar9300_set_radar_dc_thresh(struct ath_hal *ah);
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void ar9300_disable_weak_signal(struct ath_hal *ah);
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void ar9300_disable_strong_signal(struct ath_hal *ah);
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void ar9300_prep_spectral_scan(struct ath_hal *ah);
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void ar9300_disable_dc_offset(struct ath_hal *ah);
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void ar9300_enable_cck_detect(struct ath_hal *ah);
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void
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ar9300_disable_cck(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_MODE);
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val &= ~(AR_PHY_MODE_DYN_CCK_DISABLE);
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OS_REG_WRITE(ah, AR_PHY_MODE, val);
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}
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void
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ar9300_disable_radar(struct ath_hal *ah)
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{
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u_int32_t val;
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/* Enable radar FFT */
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val = OS_REG_READ(ah, AR_PHY_RADAR_0);
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val |= AR_PHY_RADAR_0_FFT_ENA;
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/* set radar detect thresholds to max to effectively disable radar */
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val &= ~AR_PHY_RADAR_0_RRSSI;
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val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI);
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val &= ~AR_PHY_RADAR_0_HEIGHT;
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val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT);
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val &= ~(AR_PHY_RADAR_0_ENA);
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OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
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/* disable extension radar detect */
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val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
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OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
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val = OS_REG_READ(ah, AR_RX_FILTER);
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val |= (1 << 13);
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OS_REG_WRITE(ah, AR_RX_FILTER, val);
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}
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void ar9300_disable_restart(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_RESTART);
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val &= ~AR_PHY_RESTART_ENA;
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OS_REG_WRITE(ah, AR_PHY_RESTART, val);
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val = OS_REG_READ(ah, AR_PHY_RESTART);
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}
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void ar9300_set_radar_dc_thresh(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
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val &= ~AR_PHY_RADAR_DC_PWR_THRESH;
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val |= SM(MAX_RADAR_DC_PWR_THRESH, AR_PHY_RADAR_DC_PWR_THRESH);
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OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val);
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val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
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}
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void
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ar9300_disable_weak_signal(struct ath_hal *ah)
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{
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/* set firpwr to max (signed) */
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OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, 0x7f);
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OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT);
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/* set firstep to max */
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OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, 0x3f);
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/* set relpwr to max (signed) */
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OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR, 0x1f);
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OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR_SIGN_BIT);
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/* set relstep to max (signed) */
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OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP, 0x1f);
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OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT);
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/* set firpwr_low to max (signed) */
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OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR, 0x7f);
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OS_REG_CLR_BIT(
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ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT);
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/* set firstep_low to max */
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OS_REG_RMW_FIELD(
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ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, 0x3f);
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/* set relstep_low to max (signed) */
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OS_REG_RMW_FIELD(
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ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP, 0x1f);
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OS_REG_CLR_BIT(
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ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT);
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}
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void
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ar9300_disable_strong_signal(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_TIMING5);
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val |= AR_PHY_TIMING5_RSSI_THR1A_ENA;
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OS_REG_WRITE(ah, AR_PHY_TIMING5, val);
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OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_RSSI_THR1A, 0x7f);
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}
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void
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ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62)
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{
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OS_REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, thresh62);
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OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, thresh62);
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/*
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OS_REG_RMW_FIELD(ah,
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AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, thresh62);
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*/
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OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62);
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}
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static void ar9300_classify_strong_bins(struct ath_hal *ah)
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{
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OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, 0x1);
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}
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void ar9300_disable_dc_offset(struct ath_hal *ah)
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{
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OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, 0);
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}
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void ar9300_enable_cck_detect(struct ath_hal *ah)
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{
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OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, 0);
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OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, 1);
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}
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void ar9300_prep_spectral_scan(struct ath_hal *ah)
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{
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ar9300_disable_radar(ah);
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ar9300_classify_strong_bins(ah);
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ar9300_disable_dc_offset(ah);
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if (AH_PRIVATE(ah)->ah_curchan &&
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IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan))
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{ /* fast clock */
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ar9300_enable_cck_detect(ah);
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}
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#ifdef DEMO_MODE
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ar9300_disable_strong_signal(ah);
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ar9300_disable_weak_signal(ah);
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ar9300_set_radar_dc_thresh(ah);
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ar9300_set_cca_threshold(ah, MAX_CCA_THRESH);
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/*ar9300_disable_restart(ah);*/
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#endif
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OS_REG_WRITE(ah, AR_PHY_ERR, HAL_PHYERR_SPECTRAL);
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}
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//#define TEST_NOISE_PWR_WITHOUT_EEPROM 1
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#ifdef TEST_NOISE_PWR_WITHOUT_EEPROM
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struct nf_cal {
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int cal;
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int pwr;
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};
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struct nf_cal_table_t {
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int freq;
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struct nf_cal chain[AH_MAX_CHAINS];
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};
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static const struct nf_cal_table_t nf_cal_table[] =
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{
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/* ch 1 */ {2412, { {N2DBM(-101, 00), N2DBM( -94, 25)},
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{N2DBM(-107, 75), N2DBM( -99, 75)},
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} },
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/* ch 6 */ {2437, { {N2DBM(-102, 25), N2DBM( -94, 25)},
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{N2DBM(-106, 00), N2DBM( -97, 25)},
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} },
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/* ch 11 */ {2462, { {N2DBM(-101, 50), N2DBM( -95, 00)},
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{N2DBM(-105, 50), N2DBM( -98, 00)},
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} },
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/* ch 36 */ {5180, { {N2DBM(-114, 25), N2DBM( -95, 00)},
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{N2DBM(-114, 75), N2DBM( -94, 00)},
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} },
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/* ch 44 */ {5220, { {N2DBM(-113, 00), N2DBM( -95, 00)},
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{N2DBM(-115, 00), N2DBM( -94, 50)},
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} },
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/* ch 64 */ {5320, { {N2DBM(-113, 00), N2DBM( -95, 00)}, // not cal'ed
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{N2DBM(-115, 00), N2DBM( -94, 50)},
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} },
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/* ch 100*/ {5500, { {N2DBM(-111, 50), N2DBM( -93, 75)},
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{N2DBM(-112, 00), N2DBM( -95, 25)},
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} },
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/* ch 120*/ {5600, { {N2DBM(-111, 50), N2DBM( -93, 75)},
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{N2DBM(-112, 00), N2DBM( -95, 25)},
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} },
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/* ch 140*/ {5700, { {N2DBM(-111, 75), N2DBM( -95, 00)},
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{N2DBM(-111, 75), N2DBM( -96, 00)},
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} },
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/* ch 157*/ {5785, { {N2DBM(-112, 50), N2DBM( -94, 75)},
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{N2DBM(-111, 75), N2DBM( -95, 50)},
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} },
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/* ch 165*/ {5825, { {N2DBM(-111, 50), N2DBM( -95, 00)},
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{N2DBM(-112, 00), N2DBM( -95, 00)},
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} },
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{0}
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};
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static int
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ar9300_noise_floor_get(struct ath_hal *ah, int freq_mhz, int ch)
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{
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int i;
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for (i = 0; nf_cal_table[i].freq != 0; i++) {
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if (nf_cal_table[i + 0].freq == freq_mhz ||
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nf_cal_table[i + 1].freq > freq_mhz ||
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nf_cal_table[i + 1].freq == 0) {
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return nf_cal_table[i].chain[ch].cal;
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}
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}
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ath_hal_printf(ah,
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"%s: **Warning: device %d.%d: "
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"no nf cal offset found for freq %d chain %d\n",
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__func__, (AH_PRIVATE(ah))->ah_macVersion,
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(AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch);
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return 0;
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}
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static int
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ar9300_noise_floor_power_get(struct ath_hal *ah, int freq_mhz, int ch)
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{
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int i;
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for (i = 0; nf_cal_table[i].freq != 0; i++) {
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if (nf_cal_table[i + 0].freq == freq_mhz ||
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nf_cal_table[i + 1].freq > freq_mhz ||
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nf_cal_table[i + 1].freq == 0) {
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return nf_cal_table[i].chain[ch].pwr;
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}
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}
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ath_hal_printf(ah,
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"%s: **Warning: device %d.%d: "
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"no nf pwr offset found for freq %d chain %d\n",
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__func__, (AH_PRIVATE(ah))->ah_macVersion,
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(AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch);
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return 0;
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}
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#else
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#define ar9300_noise_floor_get(_ah,_f,_ich) ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 1/*use_cal*/)
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#define ar9300_noise_floor_power_get(_ah,_f,_ich) ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 0/*use_cal*/)
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#endif
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void
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ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
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{
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u_int32_t val;
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//uint32_t i;
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL asleep = ahp->ah_chip_full_sleep;
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//int16_t nf_buf[HAL_NUM_NF_READINGS];
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
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}
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "%s: called\n", __func__);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_fft_period=%d\n", ss->ss_fft_period);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_period=%d\n", ss->ss_period);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_count=%d\n", ss->ss_count);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_short_report=%d\n", ss->ss_short_report);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_spectral_pri=%d\n", ss->ss_spectral_pri);
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ar9300_prep_spectral_scan(ah);
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#if 0
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if (ss->ss_spectral_pri) {
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for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
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nf_buf[i] = NOISE_PWR_DBM_2_INT(ss->ss_nf_cal[i]);
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}
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ar9300_load_nf(ah, nf_buf);
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#ifdef DEMO_MODE
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ar9300_disable_strong_signal(ah);
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ar9300_disable_weak_signal(ah);
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ar9300_set_radar_dc_thresh(ah);
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ar9300_set_cca_threshold(ah, MAX_CCA_THRESH);
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/*ar9300_disable_restart(ah);*/
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#endif
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}
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#endif
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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if (ss->ss_fft_period != HAL_SPECTRAL_PARAM_NOVAL) {
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val &= ~AR_PHY_SPECTRAL_SCAN_FFT_PERIOD;
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val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
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}
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if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
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val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
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val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
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}
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if (ss->ss_count != HAL_SPECTRAL_PARAM_NOVAL) {
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val &= ~AR_PHY_SPECTRAL_SCAN_COUNT;
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/* Remnants of a Merlin bug, 128 translates to 0 for
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* continuous scanning. Instead we do piecemeal captures
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* of 64 samples for Osprey.
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*/
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if (ss->ss_count == 128) {
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val |= SM(0, AR_PHY_SPECTRAL_SCAN_COUNT);
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} else {
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val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT);
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}
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}
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if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
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val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
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val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
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}
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if (ss->ss_short_report != HAL_SPECTRAL_PARAM_NOVAL) {
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if (ss->ss_short_report == AH_TRUE) {
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val |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
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} else {
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val &= ~AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
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}
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}
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/* if noise power cal, force high priority */
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if (ss->ss_spectral_pri != HAL_SPECTRAL_PARAM_NOVAL) {
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if (ss->ss_spectral_pri) {
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val |= AR_PHY_SPECTRAL_SCAN_PRIORITY_HI;
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} else {
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val &= ~AR_PHY_SPECTRAL_SCAN_PRIORITY_HI;
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}
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}
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/* enable spectral scan */
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OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val | AR_PHY_SPECTRAL_SCAN_ENABLE);
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
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}
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}
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/*
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* Get the spectral parameter values and return them in the pe
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* structure
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*/
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void
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ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
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{
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u_int32_t val;
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HAL_CHANNEL_INTERNAL *chan = NULL;
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const struct ieee80211_channel *c;
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int i, ichain, rx_chain_status;
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL asleep = ahp->ah_chip_full_sleep;
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "%s: called\n", __func__);
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c = AH_PRIVATE(ah)->ah_curchan;
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if (c != NULL)
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chan = ath_hal_checkchannel(ah, c);
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// XXX TODO: just always wake up all chips?
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
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}
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
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ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD);
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ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT);
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ss->ss_short_report = (val & AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT) ? 1:0;
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ss->ss_spectral_pri = ( val & AR_PHY_SPECTRAL_SCAN_PRIORITY_HI) ? 1:0;
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ss->ss_enabled = !! (val & AR_PHY_SPECTRAL_SCAN_ENABLE);
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ss->ss_active = !! (val & AR_PHY_SPECTRAL_SCAN_ACTIVE);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_fft_period=%d\n", ss->ss_fft_period);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_period=%d\n", ss->ss_period);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_count=%d\n", ss->ss_count);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_short_report=%d\n", ss->ss_short_report);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_spectral_pri=%d\n", ss->ss_spectral_pri);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_enabled=%d\n", ss->ss_enabled);
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "ss_active=%d\n", ss->ss_active);
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OS_MEMZERO(ss->ss_nf_cal, sizeof(ss->ss_nf_cal));
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OS_MEMZERO(ss->ss_nf_pwr, sizeof(ss->ss_nf_cal));
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ss->ss_nf_temp_data = 0;
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if (chan != NULL) {
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rx_chain_status = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK) & 0x7;
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for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
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ichain = i % 3;
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if (rx_chain_status & (1 << ichain)) {
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ss->ss_nf_cal[i] =
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ar9300_noise_floor_get(ah, chan->channel, ichain);
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ss->ss_nf_pwr[i] =
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ar9300_noise_floor_power_get(ah, chan->channel, ichain);
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}
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}
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ss->ss_nf_temp_data = OS_REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);
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} else {
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HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
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"%s: chan is NULL - no ss nf values\n", __func__);
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}
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
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}
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}
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HAL_BOOL
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ar9300_is_spectral_active(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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return MS(val, AR_PHY_SPECTRAL_SCAN_ACTIVE);
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}
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HAL_BOOL
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ar9300_is_spectral_enabled(struct ath_hal *ah)
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{
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u_int32_t val;
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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return MS(val, AR_PHY_SPECTRAL_SCAN_ENABLE);
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}
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void ar9300_start_spectral_scan(struct ath_hal *ah)
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{
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u_int32_t val;
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL asleep = ahp->ah_chip_full_sleep;
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
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}
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HALDEBUG(ah, HAL_DEBUG_SPECTRAL, "%s: called\n", __func__);
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ar9300_prep_spectral_scan(ah);
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/* activate spectral scan */
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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/* This is a hardware bug fix, the enable and active bits should
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* not be set/reset in the same write operation to the register
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*/
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if (!(val & AR_PHY_SPECTRAL_SCAN_ENABLE)) {
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val |= AR_PHY_SPECTRAL_SCAN_ENABLE;
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OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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}
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val |= AR_PHY_SPECTRAL_SCAN_ACTIVE;
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OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
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/* Reset the PHY_ERR_MASK */
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val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG);
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OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val | AR_PHY_ERR_RADAR);
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
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}
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}
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void ar9300_stop_spectral_scan(struct ath_hal *ah)
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{
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u_int32_t val;
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL asleep = ahp->ah_chip_full_sleep;
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
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}
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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/* deactivate spectral scan */
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/* HW Bug fix -- Do not disable the spectral scan
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* only turn off the active bit
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*/
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//val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE;
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val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE;
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OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH,
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ahp->ah_radar1);
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OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET,
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ahp->ah_dc_offset);
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OS_REG_WRITE(ah, AR_PHY_ERR, 0);
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if (AH_PRIVATE(ah)->ah_curchan &&
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IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan))
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{ /* fast clock */
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OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK,
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ahp->ah_disable_cck);
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}
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val = OS_REG_READ(ah, AR_PHY_ERR);
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val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR);
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OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val);
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
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}
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}
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u_int32_t ar9300_get_spectral_config(struct ath_hal *ah)
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{
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u_int32_t val;
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_BOOL asleep = ahp->ah_chip_full_sleep;
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
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}
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val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
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if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
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ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
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}
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return val;
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}
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int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah)
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{
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int16_t nf;
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#if 0
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struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
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#endif
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if ( (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
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/* Noise floor calibration value is ready */
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nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
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} else {
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/* NF calibration is not done, return nominal value */
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nf = AH9300(ah)->nfp->nominal;
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}
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if (nf & 0x100) {
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nf = (0 - ((nf ^ 0x1ff) + 1));
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}
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return nf;
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}
|
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int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah)
|
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{
|
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int16_t nf;
|
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#if 0
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struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
|
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#endif
|
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if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
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/* Noise floor calibration value is ready */
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nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
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} else {
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/* NF calibration is not done, return nominal value */
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nf = AH9300(ah)->nfp->nominal;
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}
|
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if (nf & 0x100) {
|
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nf = (0 - ((nf ^ 0x1ff) + 1));
|
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}
|
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return nf;
|
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}
|
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#endif /* ATH_SUPPORT_SPECTRAL */
|
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//#endif
|
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|