339 lines
10 KiB
C
339 lines
10 KiB
C
/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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* All rights reserved.
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp
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*
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* $FreeBSD$
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*/
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/openfirm.h>
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#include <sparc64/pci/ofw_pci.h>
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#include <machine/cache.h>
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#include <machine/iommureg.h>
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#include <machine/ofw_bus.h>
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#include <machine/ver.h>
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#include "pcib_if.h"
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u_int8_t pci_bus_cnt;
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phandle_t *pci_bus_map;
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int pci_bus_map_sz;
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#define OPQ_NO_SWIZZLE 1
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static struct ofw_pci_quirk {
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char *opq_model;
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int opq_quirks;
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} ofw_pci_quirks[] = {
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{ "SUNW,Ultra-4", OPQ_NO_SWIZZLE },
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{ "SUNW,Ultra-1-Engine", OPQ_NO_SWIZZLE },
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};
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#define OPQ_NENT (sizeof(ofw_pci_quirks) / sizeof(ofw_pci_quirks[0]))
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static int pci_quirks;
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#define OFW_PCI_PCIBUS "pci"
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#define PCI_BUS_MAP_INC 10
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int
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ofw_pci_orb_callback(phandle_t node, u_int8_t *pintptr, int pintsz,
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u_int8_t *pregptr, int pregsz, u_int8_t **rintr, int *terminate)
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{
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struct ofw_pci_register preg;
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u_int32_t pintr, intr;
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char type[32];
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if (pintsz != sizeof(u_int32_t))
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return (-1);
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bcopy(pintptr, &pintr, sizeof(pintr));
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if ((pci_quirks & OPQ_NO_SWIZZLE) == 0 && pregsz >= sizeof(preg) &&
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OF_getprop(node, "device_type", type, sizeof(type)) != -1 &&
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strcmp(type, OFW_PCI_PCIBUS) == 0 && pintr >= 1 && pintr <= 4) {
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/*
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* Handle a quirk found on some Netra t1 models: there exist
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* PCI bridges without interrupt maps, where we apparently must
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* do the PCI swizzle and continue to map on at the parent.
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*/
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bcopy(pregptr, &preg, sizeof(preg));
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intr = (OFW_PCI_PHYS_HI_DEVICE(preg.phys_hi) + pintr + 3) %
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4 + 1;
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*rintr = malloc(sizeof(intr), M_OFWPROP, 0);
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bcopy(&intr, *rintr, sizeof(intr));
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*terminate = 0;
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return (sizeof(intr));
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}
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return (-1);
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}
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u_int32_t
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ofw_pci_route_intr(phandle_t node, u_int32_t ign)
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{
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u_int32_t rv;
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rv = ofw_bus_route_intr(node, ORIP_NOINT, ofw_pci_orb_callback);
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if (rv == ORIR_NOTFOUND)
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return (255);
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/*
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* Some machines (notably the SPARCengine Ultra AX) have no mappings
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* at all, but use complete interrupt vector number including the IGN.
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* Catch this case and remove the IGN.
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*/
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if (rv > ign)
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rv -= ign;
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return (rv);
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}
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u_int8_t
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ofw_pci_alloc_busno(phandle_t node)
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{
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phandle_t *om;
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int osz;
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u_int8_t n;
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n = pci_bus_cnt++;
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/* Establish a mapping between bus numbers and device nodes. */
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if (n >= pci_bus_map_sz) {
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osz = pci_bus_map_sz;
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om = pci_bus_map;
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pci_bus_map_sz = n + PCI_BUS_MAP_INC;
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pci_bus_map = malloc(sizeof(*pci_bus_map) * pci_bus_map_sz,
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M_DEVBUF, M_ZERO);
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if (om != NULL) {
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bcopy(om, pci_bus_map, sizeof(*om) * osz);
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free(om, M_DEVBUF);
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}
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}
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pci_bus_map[n] = node;
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return (n);
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}
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/*
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* Initialize bridge bus numbers for bridges that implement the primary,
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* secondary and subordinate bus number registers.
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*/
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void
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ofw_pci_binit(device_t busdev, struct ofw_pci_bdesc *obd)
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{
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#ifdef OFW_PCI_DEBUG
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printf("PCI-PCI bridge at %u/%u/%u: setting bus #s to %u/%u/%u\n",
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obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus,
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obd->obd_secbus, obd->obd_subbus);
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#endif /* OFW_PCI_DEBUG */
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PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
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PCIR_PRIBUS_1, obd->obd_bus, 1);
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PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
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PCIR_SECBUS_1, obd->obd_secbus, 1);
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PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
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PCIR_SUBBUS_1, obd->obd_subbus, 1);
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}
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/*
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* Walk the PCI bus hierarchy, starting with the root PCI bus and descending
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* through bridges, and initialize the interrupt line and latency timer
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* configuration registers of attached devices using firmware information,
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* as well as the the bus numbers and ranges of the bridges.
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*/
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void
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ofw_pci_init(device_t dev, phandle_t bushdl, u_int32_t ign,
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struct ofw_pci_bdesc *obd)
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{
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struct ofw_pci_register pcir;
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struct ofw_pci_bdesc subobd, *tobd;
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phandle_t node;
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char type[32];
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int i, intr, freemap;
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u_int slot, busno, func, sub, lat;
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u_int8_t clnsz;
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/* Initialize the quirk list. */
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for (i = 0; i < OPQ_NENT; i++) {
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if (strcmp(sparc64_model, ofw_pci_quirks[i].opq_model) == 0) {
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pci_quirks = ofw_pci_quirks[i].opq_quirks;
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break;
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}
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}
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if ((node = OF_child(bushdl)) == 0)
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return;
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freemap = 0;
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busno = obd->obd_secbus;
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/*
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* Compute the value to write into the cache line size register.
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* The role of the streaming cache is unclear in write invalidate
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* transfers, so it is made sure that it's line size is always reached.
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*/
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clnsz = imax(cache.ec_linesize, STRBUF_LINESZ);
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KASSERT((clnsz / STRBUF_LINESZ) * STRBUF_LINESZ == clnsz &&
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(clnsz / cache.ec_linesize) * cache.ec_linesize == clnsz &&
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(clnsz / 4) * 4 == clnsz, ("bogus cache line size %d", clnsz));
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do {
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if (node == -1)
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panic("ofw_pci_init_intr: OF_child failed");
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if (OF_getprop(node, "device_type", type, sizeof(type)) == -1)
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type[0] = '\0';
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else
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type[sizeof(type) - 1] = '\0';
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if (OF_getprop(node, "reg", &pcir, sizeof(pcir)) == -1)
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panic("ofw_pci_init: OF_getprop failed");
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slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
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func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
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if (strcmp(type, OFW_PCI_PCIBUS) == 0) {
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/*
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* This is a pci-pci bridge, initalize the bus number and
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* recurse to initialize the child bus. The hierarchy is
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* usually at most 2 levels deep, so recursion is
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* feasible.
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*/
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subobd.obd_bus = busno;
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subobd.obd_slot = slot;
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subobd.obd_func = func;
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sub = ofw_pci_alloc_busno(node);
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subobd.obd_secbus = subobd.obd_subbus = sub;
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/* Assume this bridge is mostly standard conforming. */
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subobd.obd_init = ofw_pci_binit;
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subobd.obd_super = obd;
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/*
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* Need to change all subordinate bus registers of the
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* bridges above this one now so that configuration
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* transactions will get through.
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*/
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for (tobd = obd; tobd != NULL; tobd = tobd->obd_super) {
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tobd->obd_subbus = sub;
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tobd->obd_init(dev, tobd);
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}
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subobd.obd_init(dev, &subobd);
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#ifdef OFW_PCI_DEBUG
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device_printf(dev, "%s: descending to "
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"subordinate PCI bus\n", __func__);
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#endif /* OFW_PCI_DEBUG */
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ofw_pci_init(dev, node, ign, &subobd);
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} else {
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/*
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* Initialize the latency timer register for
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* busmaster devices to work properly. This is another
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* task which the firmware does not always perform.
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* The Min_Gnt register can be used to compute it's
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* recommended value: it contains the desired latency
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* in units of 1/4 us. To calculate the correct latency
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* timer value, a bus clock of 33 and no wait states
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* should be assumed.
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*/
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lat = PCIB_READ_CONFIG(dev, busno, slot, func,
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PCIR_MINGNT, 1) * 33 / 4;
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if (lat != 0) {
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#ifdef OFW_PCI_DEBUG
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printf("device %d/%d/%d: latency timer %d -> "
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"%d\n", busno, slot, func,
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PCIB_READ_CONFIG(dev, busno, slot, func,
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PCIR_LATTIMER, 1), lat);
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#endif /* OFW_PCI_DEBUG */
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_LATTIMER, imin(lat, 255), 1);
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}
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_CACHELNSZ, clnsz / 4, 1);
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/* Initialize the intline registers. */
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if ((intr = ofw_pci_route_intr(node, ign)) != 255) {
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#ifdef OFW_PCI_DEBUG
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device_printf(dev, "%s: mapping intr for "
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"%d/%d/%d to %d (preset was %d)\n",
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__func__, busno, slot, func, intr,
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(int)PCIB_READ_CONFIG(dev, busno, slot,
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func, PCIR_INTLINE, 1));
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#endif /* OFW_PCI_DEBUG */
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_INTLINE, intr, 1);
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} else {
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#ifdef OFW_PCI_DEBUG
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device_printf(dev, "%s: no interrupt "
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"mapping found for %d/%d/%d (preset %d)\n",
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__func__, busno, slot, func,
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(int)PCIB_READ_CONFIG(dev, busno, slot,
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func, PCIR_INTLINE, 1));
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#endif /* OFW_PCI_DEBUG */
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/*
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* The firmware initializes to 0 instead of
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* 255.
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*/
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_INTLINE, 255, 1);
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}
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}
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} while ((node = OF_peer(node)) != 0);
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}
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phandle_t
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ofw_pci_find_node(int bus, int slot, int func)
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{
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phandle_t node, bnode;
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struct ofw_pci_register pcir;
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/*
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* Retrieve the bus node from the mapping that was created on
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* initialization. The bus numbers the firmware uses cannot be trusted,
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* so they might have needed to be changed and this is necessary.
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*/
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if (bus >= pci_bus_map_sz)
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return (0);
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bnode = pci_bus_map[bus];
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if (bnode == 0)
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return (0);
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for (node = OF_child(bnode); node != 0 && node != -1;
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node = OF_peer(node)) {
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if (OF_getprop(node, "reg", &pcir, sizeof(pcir)) == -1)
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continue;
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if (OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi) == slot &&
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OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi) == func)
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return (node);
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}
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return (0);
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}
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phandle_t
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ofw_pci_node(device_t dev)
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{
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return (ofw_pci_find_node(pci_get_bus(dev), pci_get_slot(dev),
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pci_get_function(dev)));
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}
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