add35ed5b8
to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
429 lines
12 KiB
C
429 lines
12 KiB
C
/*-
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of authors nor the names of its contributors may be
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* used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/mbuf.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <sys/sockio.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/ti/ti_scm.h>
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#include <arm/ti/ti_prcm.h>
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#include <arm/ti/ti_edma3.h>
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#define TI_EDMA3_NUM_TCS 3
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#define TI_EDMA3_NUM_IRQS 3
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#define TI_EDMA3_NUM_DMA_CHS 64
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#define TI_EDMA3_NUM_QDMA_CHS 8
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#define TI_EDMA3CC_PID 0x000
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#define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4))
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#define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4))
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#define TI_EDMA3CC_QDMAQNUM 0x260
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#define TI_EDMA3CC_EMCR 0x308
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#define TI_EDMA3CC_EMCRH 0x30C
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#define TI_EDMA3CC_QEMCR 0x314
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#define TI_EDMA3CC_CCERR 0x318
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#define TI_EDMA3CC_CCERRCLR 0x31C
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#define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8))
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#define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8))
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#define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4))
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#define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200))
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#define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200))
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#define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200))
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#define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200))
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#define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200))
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#define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200))
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#define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200))
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#define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200))
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#define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200))
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#define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200))
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#define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200))
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#define TI_EDMA3CC_PARAM_OFFSET 0x4000
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#define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20))
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#define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4))
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#define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4)))
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#define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4))
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#define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4)))
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#define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000))
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#define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12)
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struct ti_edma3_softc {
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device_t sc_dev;
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struct resource * mem_res[TI_EDMA3_NUM_TCS+1];
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struct resource * irq_res[TI_EDMA3_NUM_IRQS];
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void *ih_cookie[TI_EDMA3_NUM_IRQS];
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};
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static struct ti_edma3_softc *ti_edma3_sc = NULL;
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static struct resource_spec ti_edma3_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE },
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{ -1, 0, 0 }
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};
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static struct resource_spec ti_edma3_irq_spec[] = {
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ -1, 0, 0 }
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};
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/* Read/Write macros */
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#define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)
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#define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
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#define ti_edma3_tc_rd_4(c, reg) bus_read_4(ti_edma3_sc->mem_res[c+1], reg)
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#define ti_edma3_tc_wr_4(c, reg, val) bus_write_4(ti_edma3_sc->mem_res[c+1], reg, val)
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static void ti_edma3_intr_comp(void *arg);
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static void ti_edma3_intr_mperr(void *arg);
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static void ti_edma3_intr_err(void *arg);
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static struct {
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driver_intr_t *handler;
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char * description;
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} ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = {
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{ ti_edma3_intr_comp, "EDMA Completion Interrupt" },
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{ ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" },
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{ ti_edma3_intr_err, "EDMA Error Interrupt" },
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};
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static int
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ti_edma3_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ti,edma3"))
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return (ENXIO);
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device_set_desc(dev, "TI EDMA Controller");
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return (0);
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}
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static int
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ti_edma3_attach(device_t dev)
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{
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struct ti_edma3_softc *sc = device_get_softc(dev);
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uint32_t reg;
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int err;
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int i;
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if (ti_edma3_sc)
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return (ENXIO);
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ti_edma3_sc = sc;
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sc->sc_dev = dev;
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/* Request the memory resources */
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err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res);
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if (err) {
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device_printf(dev, "Error: could not allocate mem resources\n");
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return (ENXIO);
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}
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/* Request the IRQ resources */
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err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res);
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if (err) {
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device_printf(dev, "Error: could not allocate irq resources\n");
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return (ENXIO);
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}
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/* Enable Channel Controller */
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ti_prcm_clk_enable(EDMA_TPCC_CLK);
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);
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device_printf(dev, "EDMA revision %08x\n", reg);
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/* Attach interrupt handlers */
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for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) {
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err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC |
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INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler,
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sc, &sc->ih_cookie[i]);
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if (err) {
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device_printf(dev, "could not setup %s\n",
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ti_edma3_intrs[i].description);
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return (err);
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}
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}
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return (0);
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}
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static device_method_t ti_edma3_methods[] = {
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DEVMETHOD(device_probe, ti_edma3_probe),
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DEVMETHOD(device_attach, ti_edma3_attach),
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{0, 0},
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};
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static driver_t ti_edma3_driver = {
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"ti_edma3",
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ti_edma3_methods,
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sizeof(struct ti_edma3_softc),
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};
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static devclass_t ti_edma3_devclass;
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DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0);
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MODULE_DEPEND(ti_edma3, ti_prcm, 1, 1, 1);
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static void
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ti_edma3_intr_comp(void *arg)
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{
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printf("%s: unimplemented\n", __func__);
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}
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static void
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ti_edma3_intr_mperr(void *arg)
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{
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printf("%s: unimplemented\n", __func__);
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}
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static void
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ti_edma3_intr_err(void *arg)
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{
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printf("%s: unimplemented\n", __func__);
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}
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void
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ti_edma3_init(unsigned int eqn)
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{
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uint32_t reg;
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int i;
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/* on AM335x Event queue 0 is always mapped to Transfer Controller 0,
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* event queue 1 to TC2, etc. So we are asking PRCM to power on specific
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* TC based on what event queue we need to initialize */
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ti_prcm_clk_enable(EDMA_TPTC0_CLK + eqn);
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/* Clear Event Missed Regs */
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ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF);
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ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF);
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ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF);
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/* Clear Error Reg */
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ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF);
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/* Enable DMA channels 0-63 */
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ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF);
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ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF);
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for (i = 0; i < 64; i++) {
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ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5);
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}
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/* Initialize the DMA Queue Number Registers */
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for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) {
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3));
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reg &= TI_EDMA3CC_DMAQNUM_CLR(i);
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reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn);
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ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg);
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}
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/* Enable the QDMA Region access for all channels */
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ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1);
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/*Initialize QDMA Queue Number Registers */
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for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) {
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
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reg &= TI_EDMA3CC_QDMAQNUM_CLR(i);
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reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn);
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ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
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}
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}
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#ifdef notyet
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int
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ti_edma3_enable_event_intr(unsigned int ch)
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{
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uint32_t reg;
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if (ch >= TI_EDMA3_NUM_DMA_CHS)
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return (EINVAL);
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if (ch < 32) {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch);
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} else {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32));
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}
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return 0;
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}
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#endif
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int
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ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
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{
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uint32_t reg;
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if (ch >= TI_EDMA3_NUM_DMA_CHS)
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return (EINVAL);
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/* Enable the DMA channel in the DRAE/DRAEH registers */
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if (ch < 32) {
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));
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reg |= (0x01 << ch);
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ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);
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} else {
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));
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reg |= (0x01 << (ch - 32));
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ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);
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}
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/* Associate DMA Channel to Event Queue */
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));
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reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);
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reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);
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ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);
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/* Set TCC in corresponding PaRAM Entry */
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
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reg &= TI_EDMA3CC_OPT_TCC_CLR;
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reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
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ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
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return 0;
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}
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int
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ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
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{
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uint32_t reg;
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if (ch >= TI_EDMA3_NUM_DMA_CHS)
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return (EINVAL);
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/* Enable the QDMA channel in the QRAE registers */
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));
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reg |= (0x01 << ch);
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ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);
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/* Associate QDMA Channel to Event Queue */
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
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reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);
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ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
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/* Set TCC in corresponding PaRAM Entry */
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reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
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reg &= TI_EDMA3CC_OPT_TCC_CLR;
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reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
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ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
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return 0;
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}
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int
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ti_edma3_enable_transfer_manual(unsigned int ch)
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{
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if (ch >= TI_EDMA3_NUM_DMA_CHS)
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return (EINVAL);
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/* set corresponding bit in ESR/ESRH to set a event */
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if (ch < 32) {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch);
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} else {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32));
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}
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return 0;
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}
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int
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ti_edma3_enable_transfer_qdma(unsigned int ch)
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{
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if (ch >= TI_EDMA3_NUM_QDMA_CHS)
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return (EINVAL);
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/* set corresponding bit in QEESR to enable QDMA event */
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch));
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return 0;
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}
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int
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ti_edma3_enable_transfer_event(unsigned int ch)
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{
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if (ch >= TI_EDMA3_NUM_DMA_CHS)
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return (EINVAL);
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/* Clear SECR(H) & EMCR(H) to clean any previous NULL request
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* and set corresponding bit in EESR to enable DMA event */
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if(ch < 32) {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch));
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ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch));
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch));
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} else {
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32));
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ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32));
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ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32));
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}
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return 0;
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}
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void
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ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs)
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{
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bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
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(uint32_t *) prs, 8);
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|
}
|
|
|
|
void
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|
ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs)
|
|
{
|
|
bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
|
|
(uint32_t *) prs, 8);
|
|
}
|