b598de8f92
Add a comment in ahd_clear_critical_sections() about our need to leave ENBUSFREE set in SIMODE1 while single stepping. Re-arrange some delay loops so that we always perform a read after any register write and before the delay. This should make the delay loop more accurate. When completing message processing for a packetized commention, return the controller to a state where invalid non-packetized phases will still cause protocol violations. These are the same operations as those performed in the clear_target_state routine in the firmware. Now that we have a chip with working ABORTPENDING support (the 7901B), comment out the automatic use of this feature until we can adequately test it. The previous checkin updated the bug mask for the 7901B so this code was exercised. When resetting the bus, perform an ahd_flush_device_writes() call so that our reset assertion delay is acurately timed from when the reset bit is written to the controller.
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