Konstantin Belousov af95bbf5bf Intel SDM before revision 56 described the CLFLUSH instruction as only ... ordered with the MFENCE instruction. Similar weak guarantees are also specified by the AMD APM vol. 3 rev. 3.22. x86 pmap methods pmap_invalidate_cache_range() and pmap_invalidate_cache_pages() braced CLFLUSH loop with MFENCE both before and after the loop. In the revision 56 of SDM, Intel stated that all existing implementations of CLFLUSH are strict, CLFLUSH instructions execution is ordered WRT other CLFLUSH and writes. Also, the strict behaviour is made architectural. A new instruction CLFLUSHOPT (which was documented for some time in the Instruction Set Extensions Programming Reference) provides the weak behaviour which was previously attributed to CLFLUSH. Use CLFLUSHOPT when available. When CLFLUSH is used on Intel CPUs, do not execute MFENCE before and after the flushing loop. Reviewed by: alc Sponsored by: The FreeBSD Foundation		2015-10-24 21:37:47 +00:00
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acpica	If x86 CPU implementation of the MWAIT instruction reasonably	2015-05-09 12:28:48 +00:00
amd64	Intel SDM before revision 56 described the CLFLUSH instruction as only	2015-10-24 21:37:47 +00:00
cloudabi64	Refactoring: move out generic bits from cloudabi64_sysvec.c.	2015-10-22 09:07:53 +00:00
conf	Remove compatibility shims for legacy ATA device names.	2015-10-11 13:01:51 +00:00
ia32	Remove several write-only variables, all reported by the gcc 4.9	2015-05-29 13:24:17 +00:00
include	Add CLFLUSHOPT instruction wrappers.	2015-10-23 11:45:38 +00:00
linux	Regen for linux32 rename and linux64 systrace.	2015-10-22 21:33:37 +00:00
linux32	Regen for linux32 rename and linux64 systrace.	2015-10-22 21:33:37 +00:00
pci
vmm	Move the 'devmem' device nodes from /dev/vmm to /dev/vmm.io	2015-07-06 19:41:43 +00:00
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