718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
114 lines
4.4 KiB
C
114 lines
4.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006 Juniper Networks
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_IC_QUICC_H_
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#define _DEV_IC_QUICC_H_
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/*
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* Device parameter RAM
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*/
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#define QUICC_PRAM_BASE 0x8000
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#define QUICC_PRAM_REV_NUM (QUICC_PRAM_BASE + 0xaf0)
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/* SCC parameter RAM. */
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#define QUICC_PRAM_SIZE_SCC 256
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#define QUICC_PRAM_BASE_SCC(u) (QUICC_PRAM_BASE + QUICC_PRAM_SIZE_SCC * (u))
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/* SCC parameters that are common for all modes. */
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#define QUICC_PRAM_SCC_RBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x00)
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#define QUICC_PRAM_SCC_TBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x02)
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#define QUICC_PRAM_SCC_RFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x04)
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#define QUICC_PRAM_SCC_TFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x05)
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#define QUICC_PRAM_SCC_MRBLR(u) (QUICC_PRAM_BASE_SCC(u) + 0x06)
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#define QUICC_PRAM_SCC_RBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x10)
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#define QUICC_PRAM_SCC_TBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x20)
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/*
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* SCC parameters that are specific to UART/ASYNC mode.
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*/
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#define QUICC_PRAM_SIZE_SCC_UART 0x68 /* Rounded up. */
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#define QUICC_PRAM_SCC_UART_MAX_IDL(u) (QUICC_PRAM_BASE_SCC(u) + 0x38)
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#define QUICC_PRAM_SCC_UART_IDLC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3a)
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#define QUICC_PRAM_SCC_UART_BRKCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x3c)
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#define QUICC_PRAM_SCC_UART_PAREC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3e)
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#define QUICC_PRAM_SCC_UART_FRMEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x40)
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#define QUICC_PRAM_SCC_UART_NOSEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x42)
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#define QUICC_PRAM_SCC_UART_BRKEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x44)
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#define QUICC_PRAM_SCC_UART_BRKLN(u) (QUICC_PRAM_BASE_SCC(u) + 0x46)
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#define QUICC_PRAM_SCC_UART_UADDR1(u) (QUICC_PRAM_BASE_SCC(u) + 0x48)
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#define QUICC_PRAM_SCC_UART_UADDR2(u) (QUICC_PRAM_BASE_SCC(u) + 0x4a)
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#define QUICC_PRAM_SCC_UART_TOSEQ(u) (QUICC_PRAM_BASE_SCC(u) + 0x4e)
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#define QUICC_PRAM_SCC_UART_CC(u,n) (QUICC_PRAM_BASE_SCC(u) + 0x50 + (n)*2)
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#define QUICC_PRAM_SCC_UART_RCCM(u) (QUICC_PRAM_BASE_SCC(u) + 0x60)
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#define QUICC_PRAM_SCC_UART_RCCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x62)
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#define QUICC_PRAM_SCC_UART_RLBC(u) (QUICC_PRAM_BASE_SCC(u) + 0x64)
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/*
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* Interrupt controller.
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*/
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#define QUICC_REG_SICR 0x10c00
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#define QUICC_REG_SIVEC 0x10c04
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#define QUICC_REG_SIPNR_H 0x10c08
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#define QUICC_REG_SIPNR_L 0x10c0c
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#define QUICC_REG_SCPRR_H 0x10c14
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#define QUICC_REG_SCPRR_L 0x10c18
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#define QUICC_REG_SIMR_H 0x10c1c
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#define QUICC_REG_SIMR_L 0x10c20
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#define QUICC_REG_SIEXR 0x10c24
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/*
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* System clock control register.
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*/
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#define QUICC_REG_SCCR 0x10c80
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/*
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* Baudrate generator registers.
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*/
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#define QUICC_REG_BRG(u) (0x119f0 + ((u) & 3) * 4 - ((u) & 4) * 0x100)
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/*
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* SCC registers.
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*/
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#define QUICC_REG_SIZE_SCC 0x20
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#define QUICC_REG_BASE_SCC(u) (0x11a00 + QUICC_REG_SIZE_SCC * (u))
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#define QUICC_REG_SCC_GSMR_L(u) (QUICC_REG_BASE_SCC(u) + 0x00)
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#define QUICC_REG_SCC_GSMR_H(u) (QUICC_REG_BASE_SCC(u) + 0x04)
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#define QUICC_REG_SCC_PSMR(u) (QUICC_REG_BASE_SCC(u) + 0x08)
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#define QUICC_REG_SCC_TODR(u) (QUICC_REG_BASE_SCC(u) + 0x0c)
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#define QUICC_REG_SCC_DSR(u) (QUICC_REG_BASE_SCC(u) + 0x0e)
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#define QUICC_REG_SCC_SCCE(u) (QUICC_REG_BASE_SCC(u) + 0x10)
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#define QUICC_REG_SCC_SCCM(u) (QUICC_REG_BASE_SCC(u) + 0x14)
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#define QUICC_REG_SCC_SCCS(u) (QUICC_REG_BASE_SCC(u) + 0x17)
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#endif /* _DEV_IC_QUICC_H_ */
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