1023 lines
27 KiB
C
1023 lines
27 KiB
C
/*-
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* Copyright 2006-2007 by Juniper Networks.
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* Copyright 2008 Semihalf.
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* Copyright 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Semihalf
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#define REG_CFG_ADDR 0x0000
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#define CONFIG_ACCESS_ENABLE 0x80000000
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#define REG_CFG_DATA 0x0004
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#define REG_INT_ACK 0x0008
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#define REG_POTAR(n) (0x0c00 + 0x20 * (n))
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#define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
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#define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
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#define REG_POWAR(n) (0x0c10 + 0x20 * (n))
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#define REG_PITAR(n) (0x0e00 - 0x20 * (n))
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#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
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#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
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#define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
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#define REG_PEX_MES_DR 0x0020
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#define REG_PEX_MES_IER 0x0028
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#define REG_PEX_ERR_DR 0x0e00
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#define REG_PEX_ERR_EN 0x0e08
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#define PCIR_LTSSM 0x404
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#define LTSSM_STAT_L0 0x16
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#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
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struct fsl_pcib_softc {
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device_t sc_dev;
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struct rman sc_iomem;
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bus_addr_t sc_iomem_va; /* Virtual mapping. */
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bus_addr_t sc_iomem_size;
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bus_addr_t sc_iomem_alloc; /* Next allocation. */
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int sc_iomem_target;
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struct rman sc_ioport;
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bus_addr_t sc_ioport_va; /* Virtual mapping. */
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bus_addr_t sc_ioport_size;
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bus_addr_t sc_ioport_alloc; /* Next allocation. */
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int sc_ioport_target;
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struct resource *sc_res;
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bus_space_handle_t sc_bsh;
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bus_space_tag_t sc_bst;
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int sc_rid;
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int sc_busnr;
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int sc_pcie;
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uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
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/* Devices that need special attention. */
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int sc_devfn_tundra;
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int sc_devfn_via_ide;
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struct fdt_pci_intr sc_intr_info;
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};
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/* Local forward declerations. */
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static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
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u_int, int);
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static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
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u_int, uint32_t, int);
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static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
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static void fsl_pcib_err_init(device_t);
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static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
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u_long, u_long);
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static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
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static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *);
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static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long,
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u_long);
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static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long,
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u_long, u_long);
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/* Forward declerations. */
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static int fsl_pcib_attach(device_t);
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static int fsl_pcib_detach(device_t);
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static int fsl_pcib_probe(device_t);
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static struct resource *fsl_pcib_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int fsl_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
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static int fsl_pcib_release_resource(device_t, device_t, int, int,
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struct resource *);
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static int fsl_pcib_write_ivar(device_t, device_t, int, uintptr_t);
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static int fsl_pcib_maxslots(device_t);
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static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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/* Configuration r/w mutex. */
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struct mtx pcicfg_mtx;
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static int mtx_initialized = 0;
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/*
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* Bus interface definitions.
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*/
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static device_method_t fsl_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, fsl_pcib_probe),
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DEVMETHOD(device_attach, fsl_pcib_attach),
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DEVMETHOD(device_detach, fsl_pcib_detach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, fsl_pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, fsl_pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, fsl_pcib_alloc_resource),
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DEVMETHOD(bus_release_resource, fsl_pcib_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
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DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
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DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
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/* OFW bus interface */
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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{ 0, 0 }
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};
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static driver_t fsl_pcib_driver = {
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"pcib",
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fsl_pcib_methods,
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sizeof(struct fsl_pcib_softc),
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};
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devclass_t pcib_devclass;
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DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0);
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static int
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fsl_pcib_probe(device_t dev)
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{
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phandle_t node;
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node = ofw_bus_get_node(dev);
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if (!fdt_is_type(node, "pci"))
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return (ENXIO);
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if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") ||
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fdt_is_compatible(node, "fsl,mpc8548-pcie")))
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return (ENXIO);
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device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fsl_pcib_attach(device_t dev)
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{
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struct fsl_pcib_softc *sc;
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phandle_t node;
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uint32_t cfgreg;
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int maxslot;
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uint8_t ltssm, capptr;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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RF_ACTIVE);
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if (sc->sc_res == NULL) {
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device_printf(dev, "could not map I/O memory\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res);
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sc->sc_busnr = 0;
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if (!mtx_initialized) {
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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mtx_initialized = 1;
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}
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cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
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if (cfgreg != 0x1057 && cfgreg != 0x1957)
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goto err;
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capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
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while (capptr != 0) {
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cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
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switch (cfgreg & 0xff) {
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case PCIY_PCIX:
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break;
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case PCIY_EXPRESS:
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sc->sc_pcie = 1;
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sc->sc_pcie_capreg = capptr;
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break;
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}
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capptr = (cfgreg >> 8) & 0xff;
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}
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node = ofw_bus_get_node(dev);
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/*
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* Get PCI interrupt info.
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*/
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if (fsl_pcib_intr_info(node, sc) != 0) {
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device_printf(dev, "could not retrieve interrupt info\n");
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goto err;
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}
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/*
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* Configure decode windows for PCI(E) access.
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*/
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if (fsl_pcib_decode_win(node, sc) != 0)
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goto err;
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cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
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cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
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PCIM_CMD_PORTEN;
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fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
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sc->sc_devfn_tundra = -1;
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sc->sc_devfn_via_ide = -1;
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/*
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* Scan bus using firmware configured, 0 based bus numbering.
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*/
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sc->sc_busnr = 0;
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maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
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fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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if (sc->sc_pcie) {
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ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
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if (ltssm < LTSSM_STAT_L0) {
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if (bootverbose)
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printf("PCI %d: no PCIE link, skipping\n",
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device_get_unit(dev));
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return (0);
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}
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}
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fsl_pcib_err_init(dev);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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err:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (ENXIO);
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}
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static uint32_t
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fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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uint32_t addr, data;
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if (bus == sc->sc_busnr - 1)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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addr |= (func & 0x7) << 8;
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addr |= reg & 0xfc;
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if (sc->sc_pcie)
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addr |= (reg & 0xf00) << 16;
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mtx_lock_spin(&pcicfg_mtx);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
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switch (bytes) {
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case 1:
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data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 3));
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break;
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case 2:
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data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 2)));
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break;
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case 4:
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data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA));
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break;
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default:
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data = ~0;
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break;
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}
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mtx_unlock_spin(&pcicfg_mtx);
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return (data);
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}
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static void
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fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t data, int bytes)
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{
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uint32_t addr;
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if (bus == sc->sc_busnr - 1)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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addr |= (func & 0x7) << 8;
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addr |= reg & 0xfc;
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if (sc->sc_pcie)
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addr |= (reg & 0xf00) << 16;
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mtx_lock_spin(&pcicfg_mtx);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
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switch (bytes) {
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case 1:
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bus_space_write_1(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 3), data);
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break;
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case 2:
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bus_space_write_2(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 2), htole16(data));
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break;
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case 4:
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA, htole32(data));
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break;
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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#if 0
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static void
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dump(struct fsl_pcib_softc *sc)
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{
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unsigned int i;
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#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
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for (i = 0; i < 5; i++) {
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printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
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printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
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printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
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printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
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}
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printf("\n");
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for (i = 1; i < 4; i++) {
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printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
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printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
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printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
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printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
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}
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printf("\n");
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#undef RD
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for (i = 0; i < 0x48; i += 4) {
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printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
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i, 4));
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}
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}
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#endif
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static int
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fsl_pcib_maxslots(device_t dev)
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{
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struct fsl_pcib_softc *sc = device_get_softc(dev);
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return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
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}
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static uint32_t
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fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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struct fsl_pcib_softc *sc = device_get_softc(dev);
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u_int devfn;
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if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
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return (~0);
|
|
devfn = DEVFN(bus, slot, func);
|
|
if (devfn == sc->sc_devfn_tundra)
|
|
return (~0);
|
|
if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
|
|
return (1);
|
|
return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
|
|
}
|
|
|
|
static void
|
|
fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
|
u_int reg, uint32_t val, int bytes)
|
|
{
|
|
struct fsl_pcib_softc *sc = device_get_softc(dev);
|
|
|
|
if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
|
|
return;
|
|
fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
|
|
}
|
|
|
|
static void
|
|
fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
|
|
int slot, int fn)
|
|
{
|
|
|
|
if (device == 0x0686) {
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
|
|
} else if (device == 0x0571) {
|
|
sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
|
|
}
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
|
|
int barno)
|
|
{
|
|
bus_addr_t *allocp;
|
|
uint32_t addr, mask, size;
|
|
int reg, width;
|
|
|
|
reg = PCIR_BAR(barno);
|
|
|
|
if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
|
|
switch (barno) {
|
|
case 0: addr = 0x1f0; break;
|
|
case 1: addr = 0x3f4; break;
|
|
case 2: addr = 0x170; break;
|
|
case 3: addr = 0x374; break;
|
|
case 4: addr = 0xcc0; break;
|
|
default: return (1);
|
|
}
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
|
|
return (1);
|
|
}
|
|
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
|
|
size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
|
|
if (size == 0)
|
|
return (1);
|
|
width = ((size & 7) == 4) ? 2 : 1;
|
|
|
|
if (size & 1) { /* I/O port */
|
|
allocp = &sc->sc_ioport_alloc;
|
|
size &= ~3;
|
|
if ((size & 0xffff0000) == 0)
|
|
size |= 0xffff0000;
|
|
} else { /* memory */
|
|
allocp = &sc->sc_iomem_alloc;
|
|
size &= ~15;
|
|
}
|
|
mask = ~size;
|
|
size = mask + 1;
|
|
/* Sanity check (must be a power of 2). */
|
|
if (size & mask)
|
|
return (width);
|
|
|
|
addr = (*allocp + mask) & ~mask;
|
|
*allocp = addr + size;
|
|
|
|
if (bootverbose)
|
|
printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
|
|
device_get_unit(sc->sc_dev), bus, slot, func, reg,
|
|
size, addr);
|
|
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
|
|
if (width == 2)
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
|
|
0, 4);
|
|
return (width);
|
|
}
|
|
|
|
static u_int
|
|
fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
|
|
u_int intpin)
|
|
{
|
|
int err, unit;
|
|
u_int devfn, intline;
|
|
|
|
unit = device_get_unit(sc->sc_dev);
|
|
|
|
devfn = DEVFN(bus, slot, func);
|
|
if (devfn == sc->sc_devfn_via_ide)
|
|
intline = MAP_IRQ(0, 14);
|
|
else if (devfn == sc->sc_devfn_via_ide + 1)
|
|
intline = MAP_IRQ(0, 10);
|
|
else if (devfn == sc->sc_devfn_via_ide + 2)
|
|
intline = MAP_IRQ(0, 10);
|
|
else {
|
|
if (intpin != 0)
|
|
err = fdt_pci_route_intr(bus, slot, func, intpin,
|
|
&sc->sc_intr_info, &intline);
|
|
else
|
|
intline = 0xff;
|
|
}
|
|
|
|
if (bootverbose)
|
|
printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n",
|
|
unit, bus, slot, func, intpin, intline);
|
|
|
|
return (intline);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
|
|
{
|
|
int secbus;
|
|
int old_pribus, old_secbus, old_subbus;
|
|
int new_pribus, new_secbus, new_subbus;
|
|
int slot, func, maxfunc;
|
|
int bar, maxbar;
|
|
uint16_t vendor, device;
|
|
uint8_t command, hdrtype, class, subclass;
|
|
uint8_t intline, intpin;
|
|
|
|
secbus = bus;
|
|
for (slot = 0; slot <= maxslot; slot++) {
|
|
maxfunc = 0;
|
|
for (func = 0; func <= maxfunc; func++) {
|
|
hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_HDRTYPE, 1);
|
|
|
|
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
|
|
continue;
|
|
|
|
if (func == 0 && (hdrtype & PCIM_MFDEV))
|
|
maxfunc = PCI_FUNCMAX;
|
|
|
|
vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_VENDOR, 2);
|
|
device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_DEVICE, 2);
|
|
|
|
if (vendor == 0x1957 && device == 0x3fff) {
|
|
sc->sc_devfn_tundra = DEVFN(bus, slot, func);
|
|
continue;
|
|
}
|
|
|
|
command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_COMMAND, 1);
|
|
command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_COMMAND, command, 1);
|
|
|
|
if (vendor == 0x1106)
|
|
fsl_pcib_init_via(sc, device, bus, slot, func);
|
|
|
|
/* Program the base address registers. */
|
|
maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
|
|
bar = 0;
|
|
while (bar < maxbar)
|
|
bar += fsl_pcib_init_bar(sc, bus, slot, func,
|
|
bar);
|
|
|
|
/* Perform interrupt routing. */
|
|
intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_INTPIN, 1);
|
|
intline = fsl_pcib_route_int(sc, bus, slot, func,
|
|
intpin);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_INTLINE, intline, 1);
|
|
|
|
command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_COMMAND, command, 1);
|
|
|
|
/*
|
|
* Handle PCI-PCI bridges
|
|
*/
|
|
class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_CLASS, 1);
|
|
subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_SUBCLASS, 1);
|
|
|
|
/* Allow only proper PCI-PCI briges */
|
|
if (class != PCIC_BRIDGE)
|
|
continue;
|
|
if (subclass != PCIS_BRIDGE_PCI)
|
|
continue;
|
|
|
|
secbus++;
|
|
|
|
/* Program I/O decoder. */
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
|
|
|
|
/* Program (non-prefetchable) memory decoder. */
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
|
|
|
|
/* Program prefetchable memory decoder. */
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMBASEL_1, 0x0010, 2);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMLIMITL_1, 0x000f, 2);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMBASEH_1, 0x00000000, 4);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMLIMITH_1, 0x00000000, 4);
|
|
|
|
/* Read currect bus register configuration */
|
|
old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
|
|
slot, func, PCIR_PRIBUS_1, 1);
|
|
old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
|
|
slot, func, PCIR_SECBUS_1, 1);
|
|
old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
|
|
slot, func, PCIR_SUBBUS_1, 1);
|
|
|
|
if (bootverbose)
|
|
printf("PCI: reading firmware bus numbers for "
|
|
"secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
|
|
secbus, old_pribus, old_secbus, old_subbus);
|
|
|
|
new_pribus = bus;
|
|
new_secbus = secbus;
|
|
|
|
secbus = fsl_pcib_init(sc, secbus,
|
|
(subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
|
|
|
|
new_subbus = secbus;
|
|
|
|
if (bootverbose)
|
|
printf("PCI: translate firmware bus numbers "
|
|
"for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
|
|
secbus, old_pribus, old_secbus, old_subbus,
|
|
new_pribus, new_secbus, new_subbus);
|
|
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PRIBUS_1, new_pribus, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SECBUS_1, new_secbus, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SUBBUS_1, new_subbus, 1);
|
|
}
|
|
}
|
|
|
|
return (secbus);
|
|
}
|
|
|
|
static void
|
|
fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start,
|
|
u_long size, u_long pci_start)
|
|
{
|
|
uint32_t attr, bar, tar;
|
|
|
|
KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
|
|
|
|
switch (tgt) {
|
|
/* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
|
|
case OCP85XX_TGTIF_RAM1:
|
|
attr = 0xa0f55000 | (ffsl(size) - 2);
|
|
break;
|
|
default:
|
|
attr = 0;
|
|
break;
|
|
}
|
|
tar = start >> 12;
|
|
bar = pci_start >> 12;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
|
|
}
|
|
|
|
static void
|
|
fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start,
|
|
u_long size, u_long pci_start)
|
|
{
|
|
uint32_t attr, bar, tar;
|
|
|
|
switch (res) {
|
|
case SYS_RES_MEMORY:
|
|
attr = 0x80044000 | (ffsl(size) - 2);
|
|
break;
|
|
case SYS_RES_IOPORT:
|
|
attr = 0x80088000 | (ffsl(size) - 2);
|
|
break;
|
|
default:
|
|
attr = 0x0004401f;
|
|
break;
|
|
}
|
|
bar = start >> 12;
|
|
tar = pci_start >> 12;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_set_range(struct fsl_pcib_softc *sc, int type, int wnd, u_long start,
|
|
u_long size)
|
|
{
|
|
struct rman *rm;
|
|
u_long end, alloc;
|
|
bus_addr_t pci_start, pci_end;
|
|
bus_addr_t *vap, *allocp;
|
|
int error;
|
|
|
|
end = start + size - 1;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IOPORT:
|
|
rm = &sc->sc_ioport;
|
|
pci_start = 0x0000;
|
|
pci_end = 0xffff;
|
|
alloc = 0x1000;
|
|
vap = &sc->sc_ioport_va;
|
|
allocp = &sc->sc_ioport_alloc;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm = &sc->sc_iomem;
|
|
pci_start = start;
|
|
pci_end = end;
|
|
alloc = 0;
|
|
vap = &sc->sc_iomem_va;
|
|
allocp = &sc->sc_iomem_alloc;
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
|
|
rm->rm_type = RMAN_ARRAY;
|
|
rm->rm_start = pci_start;
|
|
rm->rm_end = pci_end;
|
|
error = rman_init(rm);
|
|
if (error)
|
|
return (error);
|
|
|
|
error = rman_manage_region(rm, pci_start, pci_end);
|
|
if (error) {
|
|
rman_fini(rm);
|
|
return (error);
|
|
}
|
|
|
|
*allocp = pci_start + alloc;
|
|
*vap = (uintptr_t)pmap_mapdev(start, size);
|
|
fsl_pcib_outbound(sc, wnd, type, start, size, pci_start);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
fsl_pcib_err_init(device_t dev)
|
|
{
|
|
struct fsl_pcib_softc *sc;
|
|
uint16_t sec_stat, dsr;
|
|
uint32_t dcr, err_en;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
|
|
if (sec_stat)
|
|
fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
|
|
if (sc->sc_pcie) {
|
|
/* Clear error bits */
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
|
|
0xffffffff);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
|
|
0xffffffff);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
|
|
0xffffffff);
|
|
|
|
dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
|
|
sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 2);
|
|
if (dsr)
|
|
fsl_pcib_cfgwrite(sc, 0, 0, 0,
|
|
sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA,
|
|
0xffff, 2);
|
|
|
|
/* Enable all errors reporting */
|
|
err_en = 0x00bfff00;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
|
|
err_en);
|
|
|
|
/* Enable error reporting: URR, FER, NFER */
|
|
dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
|
|
sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, 4);
|
|
dcr |= PCIM_EXP_CTL_URR_ENABLE | PCIM_EXP_CTL_FER_ENABLE |
|
|
PCIM_EXP_CTL_NFER_ENABLE;
|
|
fsl_pcib_cfgwrite(sc, 0, 0, 0,
|
|
sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, dcr, 4);
|
|
}
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_detach(device_t dev)
|
|
{
|
|
|
|
if (mtx_initialized) {
|
|
mtx_destroy(&pcicfg_mtx);
|
|
mtx_initialized = 0;
|
|
}
|
|
return (bus_generic_detach(dev));
|
|
}
|
|
|
|
static struct resource *
|
|
fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
struct fsl_pcib_softc *sc = device_get_softc(dev);
|
|
struct rman *rm;
|
|
struct resource *res;
|
|
bus_addr_t va;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IOPORT:
|
|
rm = &sc->sc_ioport;
|
|
va = sc->sc_ioport_va;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm = &sc->sc_iomem;
|
|
va = sc->sc_iomem_va;
|
|
break;
|
|
case SYS_RES_IRQ:
|
|
if (start < 16) {
|
|
device_printf(dev, "%s requested ISA interrupt %lu\n",
|
|
device_get_nameunit(child), start);
|
|
}
|
|
flags |= RF_SHAREABLE;
|
|
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
type, rid, start, end, count, flags));
|
|
default:
|
|
return (NULL);
|
|
}
|
|
|
|
res = rman_reserve_resource(rm, start, end, count, flags, child);
|
|
if (res == NULL)
|
|
return (NULL);
|
|
|
|
rman_set_bustag(res, &bs_le_tag);
|
|
rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start);
|
|
return (res);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
|
|
return (rman_release_resource(res));
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
|
{
|
|
struct fsl_pcib_softc *sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
*result = sc->sc_busnr;
|
|
return (0);
|
|
case PCIB_IVAR_DOMAIN:
|
|
*result = device_get_unit(dev);
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
|
|
{
|
|
struct fsl_pcib_softc *sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
sc->sc_busnr = value;
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_intr_info(phandle_t node, struct fsl_pcib_softc *sc)
|
|
{
|
|
int error;
|
|
|
|
if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
|
|
return (error);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
|
|
{
|
|
struct fdt_pci_range io_space, mem_space;
|
|
device_t dev;
|
|
int error;
|
|
|
|
dev = sc->sc_dev;
|
|
|
|
if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
|
|
device_printf(dev, "could not retrieve 'ranges' data\n");
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Configure LAW decode windows.
|
|
*/
|
|
error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
|
|
&sc->sc_ioport_target);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not retrieve PCI LAW target info\n");
|
|
return (error);
|
|
}
|
|
error = law_enable(sc->sc_iomem_target, mem_space.base_parent,
|
|
mem_space.len);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not program LAW for PCI MEM range\n");
|
|
return (error);
|
|
}
|
|
error = law_enable(sc->sc_ioport_target, io_space.base_parent,
|
|
io_space.len);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not program LAW for PCI IO range\n");
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Set outbout and inbound windows.
|
|
*/
|
|
fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
|
|
if ((error = fsl_pcib_set_range(sc, SYS_RES_MEMORY, 1,
|
|
mem_space.base_parent, mem_space.len)) != 0)
|
|
return (error);
|
|
if ((error = fsl_pcib_set_range(sc, SYS_RES_IOPORT, 2,
|
|
io_space.base_parent, io_space.len)) != 0)
|
|
return (error);
|
|
|
|
fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
|
|
fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
|
|
|
|
fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
|
|
fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
|
|
fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
|
|
2U * 1024U * 1024U * 1024U, 0);
|
|
|
|
return (0);
|
|
}
|