329e817fcc
Remove unused and easy to misuse PNP macro parameter Inspired by r338025, just remove the element size parameter to the MODULE_PNP_INFO macro entirely. The 'table' parameter is now required to have correct pointer (or array) type. Since all invocations of the macro already had this property and the emitted PNP data continues to include the element size, there is no functional change. Mostly done with the coccinelle 'spatch' tool: $ cat modpnpsize0.cocci @normaltables@ identifier b,c; expression a,d,e; declarer MODULE_PNP_INFO; @@ MODULE_PNP_INFO(a,b,c,d, -sizeof(d[0]), e); @singletons@ identifier b,c,d; expression a; declarer MODULE_PNP_INFO; @@ MODULE_PNP_INFO(a,b,c,&d, -sizeof(d), 1); $ rg -l MODULE_PNP_INFO -- sys | \ xargs spatch --in-place --sp-file modpnpsize0.cocci (Note that coccinelle invokes diff(1) via a PATH search and expects diff to tolerate the -B flag, which BSD diff does not. So I had to link gdiff into PATH as diff to use spatch.) Tinderbox'd (-DMAKE_JUST_KERNELS). Approved by: re (glen)
375 lines
11 KiB
C
375 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-NetBSD
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*
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* Copyright (C) 2001 Eduardo Horvath.
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* Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: if_gem_pci.c,v 1.7 2001/10/18 15:09:15 thorpej Exp
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* PCI bindings for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <machine/bus.h>
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#if defined(__powerpc__) || defined(__sparc64__)
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/ofw_machdep.h>
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#endif
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#include <machine/resource.h>
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#include <dev/gem/if_gemreg.h>
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#include <dev/gem/if_gemvar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "miibus_if.h"
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static int gem_pci_attach(device_t dev);
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static int gem_pci_detach(device_t dev);
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static int gem_pci_probe(device_t dev);
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static int gem_pci_resume(device_t dev);
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static int gem_pci_suspend(device_t dev);
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static const struct gem_pci_dev {
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uint32_t gpd_devid;
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int gpd_variant;
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const char *gpd_desc;
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} gem_pci_devlist[] = {
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{ 0x1101108e, GEM_SUN_ERI, "Sun ERI 10/100 Ethernet" },
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{ 0x2bad108e, GEM_SUN_GEM, "Sun GEM Gigabit Ethernet" },
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{ 0x0021106b, GEM_APPLE_GMAC, "Apple UniNorth GMAC Ethernet" },
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{ 0x0024106b, GEM_APPLE_GMAC, "Apple Pangea GMAC Ethernet" },
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{ 0x0032106b, GEM_APPLE_GMAC, "Apple UniNorth2 GMAC Ethernet" },
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{ 0x004c106b, GEM_APPLE_K2_GMAC,"Apple K2 GMAC Ethernet" },
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{ 0x0051106b, GEM_APPLE_GMAC, "Apple Shasta GMAC Ethernet" },
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{ 0x006b106b, GEM_APPLE_GMAC, "Apple Intrepid 2 GMAC Ethernet" },
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{ 0, 0, NULL }
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};
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static device_method_t gem_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, gem_pci_probe),
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DEVMETHOD(device_attach, gem_pci_attach),
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DEVMETHOD(device_detach, gem_pci_detach),
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DEVMETHOD(device_suspend, gem_pci_suspend),
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DEVMETHOD(device_resume, gem_pci_resume),
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/* Use the suspend handler here, it is all that is required. */
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DEVMETHOD(device_shutdown, gem_pci_suspend),
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/* MII interface */
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DEVMETHOD(miibus_readreg, gem_mii_readreg),
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DEVMETHOD(miibus_writereg, gem_mii_writereg),
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DEVMETHOD(miibus_statchg, gem_mii_statchg),
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DEVMETHOD_END
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};
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static driver_t gem_pci_driver = {
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"gem",
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gem_pci_methods,
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sizeof(struct gem_softc)
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};
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DRIVER_MODULE(gem, pci, gem_pci_driver, gem_devclass, 0, 0);
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MODULE_PNP_INFO("W32:vendor/device", pci, gem, gem_pci_devlist,
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nitems(gem_pci_devlist) - 1);
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MODULE_DEPEND(gem, pci, 1, 1, 1);
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MODULE_DEPEND(gem, ether, 1, 1, 1);
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static int
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gem_pci_probe(device_t dev)
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{
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int i;
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for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
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if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
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device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
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return (BUS_PROBE_DEFAULT);
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}
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}
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return (ENXIO);
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}
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static struct resource_spec gem_pci_res_spec[] = {
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{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* GEM_RES_INTR */
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* GEM_RES_BANK1 */
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{ -1, 0 }
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};
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#define GEM_SHARED_PINS "shared-pins"
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#define GEM_SHARED_PINS_SERDES "serdes"
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static int
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gem_pci_attach(device_t dev)
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{
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struct gem_softc *sc;
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int i;
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#if defined(__powerpc__) || defined(__sparc64__)
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char buf[sizeof(GEM_SHARED_PINS)];
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#else
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int j;
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#endif
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sc = device_get_softc(dev);
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sc->sc_variant = GEM_UNKNOWN;
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for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
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if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
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sc->sc_variant = gem_pci_devlist[i].gpd_variant;
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break;
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}
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}
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if (sc->sc_variant == GEM_UNKNOWN) {
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device_printf(dev, "unknown adaptor\n");
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return (ENXIO);
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}
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pci_enable_busmaster(dev);
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/*
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* Some Sun GEMs/ERIs do have their intpin register bogusly set to 0,
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* although it should be 1. Correct that.
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*/
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if (pci_get_intpin(dev) == 0)
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pci_set_intpin(dev, 1);
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/* Set the PCI latency timer for Sun ERIs. */
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if (sc->sc_variant == GEM_SUN_ERI)
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pci_write_config(dev, PCIR_LATTIMER, GEM_ERI_LATENCY_TIMER, 1);
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sc->sc_dev = dev;
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sc->sc_flags |= GEM_PCI;
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if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
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device_printf(dev, "failed to allocate resources\n");
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bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
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return (ENXIO);
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}
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GEM_LOCK_INIT(sc, device_get_nameunit(dev));
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/*
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* Derive GEM_RES_BANK2 from GEM_RES_BANK1. This seemed cleaner
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* with the old way of using copies of the bus tag and handle in
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* the softc along with bus_space_*()...
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*/
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sc->sc_res[GEM_RES_BANK2] = malloc(sizeof(*sc->sc_res[GEM_RES_BANK2]),
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M_DEVBUF, M_NOWAIT | M_ZERO);
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if (sc->sc_res[GEM_RES_BANK2] == NULL) {
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device_printf(dev, "failed to allocate bank2 resource\n");
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goto fail;
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}
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rman_set_bustag(sc->sc_res[GEM_RES_BANK2],
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rman_get_bustag(sc->sc_res[GEM_RES_BANK1]));
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bus_space_subregion(rman_get_bustag(sc->sc_res[GEM_RES_BANK1]),
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rman_get_bushandle(sc->sc_res[GEM_RES_BANK1]),
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GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE,
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&sc->sc_res[GEM_RES_BANK2]->r_bushandle);
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/* Determine whether we're running at 66MHz. */
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if ((GEM_BANK2_READ_4(sc, GEM_PCI_BIF_CONFIG) &
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GEM_PCI_BIF_CNF_M66EN) != 0)
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sc->sc_flags |= GEM_PCI66;
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#if defined(__powerpc__) || defined(__sparc64__)
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OF_getetheraddr(dev, sc->sc_enaddr);
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if (OF_getprop(ofw_bus_get_node(dev), GEM_SHARED_PINS, buf,
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sizeof(buf)) > 0) {
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buf[sizeof(buf) - 1] = '\0';
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if (strcmp(buf, GEM_SHARED_PINS_SERDES) == 0)
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sc->sc_flags |= GEM_SERDES;
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}
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#else
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/*
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* Dig out VPD (vital product data) and read NA (network address).
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* The VPD resides in the PCI Expansion ROM (PCI FCode) and can't
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* be accessed via the PCI capability pointer.
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* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
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* chapter 2 describes the data structure.
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*/
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#define PCI_ROMHDR_SIZE 0x1c
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#define PCI_ROMHDR_SIG 0x00
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#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
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#define PCI_ROMHDR_PTR_DATA 0x18
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#define PCI_ROM_SIZE 0x18
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#define PCI_ROM_SIG 0x00
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#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
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/* reversed */
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#define PCI_ROM_VENDOR 0x04
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#define PCI_ROM_DEVICE 0x06
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#define PCI_ROM_PTR_VPD 0x08
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#define PCI_VPDRES_BYTE0 0x00
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#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
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#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
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#define PCI_VPDRES_LARGE_LEN_LSB 0x01
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#define PCI_VPDRES_LARGE_LEN_MSB 0x02
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#define PCI_VPDRES_LARGE_SIZE 0x03
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#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
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#define PCI_VPD_KEY0 0x00
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#define PCI_VPD_KEY1 0x01
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#define PCI_VPD_LEN 0x02
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#define PCI_VPD_SIZE 0x03
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#define GEM_ROM_READ_1(sc, offs) \
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GEM_BANK1_READ_1((sc), GEM_PCI_ROM_OFFSET + (offs))
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#define GEM_ROM_READ_2(sc, offs) \
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GEM_BANK1_READ_2((sc), GEM_PCI_ROM_OFFSET + (offs))
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#define GEM_ROM_READ_4(sc, offs) \
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GEM_BANK1_READ_4((sc), GEM_PCI_ROM_OFFSET + (offs))
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/* Read PCI Expansion ROM header. */
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if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
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(i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
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PCI_ROMHDR_SIZE) {
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device_printf(dev, "unexpected PCI Expansion ROM header\n");
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goto fail;
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}
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/* Read PCI Expansion ROM data. */
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if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
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GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
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GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
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(j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
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i + PCI_ROM_SIZE) {
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device_printf(dev, "unexpected PCI Expansion ROM data\n");
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goto fail;
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}
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/*
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* Read PCI VPD.
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* SUNW,pci-gem cards have a single large resource VPD-R tag
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* containing one NA. The VPD used is not in PCI 2.2 standard
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* format however. The length in the resource header is in big
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* endian and the end tag is non-standard (0x79) and followed
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* by an all-zero "checksum" byte. Sun calls this a "Fresh
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* Choice Ethernet" VPD...
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*/
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if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
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j + PCI_VPDRES_BYTE0)) == 0 ||
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PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
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j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD ||
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((GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8) |
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
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PCI_VPD_SIZE + ETHER_ADDR_LEN ||
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY0) !=
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0x4e /* N */ ||
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY1) !=
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0x41 /* A */ ||
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_LEN) !=
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ETHER_ADDR_LEN ||
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE +
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ETHER_ADDR_LEN) != 0x79) {
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device_printf(dev, "unexpected PCI VPD\n");
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goto fail;
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}
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bus_read_region_1(sc->sc_res[GEM_RES_BANK1],
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GEM_PCI_ROM_OFFSET + j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE,
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sc->sc_enaddr, ETHER_ADDR_LEN);
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#endif
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/*
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* The Xserve G5 has a fake GMAC with an all-zero MAC address.
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* Check for this, and don't attach in this case.
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*/
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for (i = 0; i < ETHER_ADDR_LEN && sc->sc_enaddr[i] == 0; i++) {}
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if (i == ETHER_ADDR_LEN) {
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device_printf(dev, "invalid MAC address\n");
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goto fail;
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}
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if (gem_attach(sc) != 0) {
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device_printf(dev, "could not be attached\n");
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goto fail;
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}
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if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET |
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INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) {
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device_printf(dev, "failed to set up interrupt\n");
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gem_detach(sc);
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goto fail;
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}
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return (0);
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fail:
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if (sc->sc_res[GEM_RES_BANK2] != NULL)
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free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
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GEM_LOCK_DESTROY(sc);
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bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
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return (ENXIO);
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}
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static int
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gem_pci_detach(device_t dev)
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{
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struct gem_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->sc_res[GEM_RES_INTR], sc->sc_ih);
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gem_detach(sc);
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free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
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GEM_LOCK_DESTROY(sc);
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bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
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return (0);
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}
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static int
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gem_pci_suspend(device_t dev)
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{
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gem_suspend(device_get_softc(dev));
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return (0);
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}
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static int
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gem_pci_resume(device_t dev)
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{
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gem_resume(device_get_softc(dev));
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return (0);
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}
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