971e53c937
2. Break transmit when IFF_DRV_RUNNING is OFF. 3. set desc_count=0 for default case in switch in ql_rcv_isr() MFC after:5 days
671 lines
16 KiB
C
671 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013-2016 Qlogic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* File: ql_ioctl.c
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* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "ql_os.h"
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#include "ql_hw.h"
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#include "ql_def.h"
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#include "ql_inline.h"
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#include "ql_glbl.h"
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#include "ql_ioctl.h"
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#include "ql_ver.h"
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#include "ql_dbg.h"
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static int ql_slowpath_log(qla_host_t *ha, qla_sp_log_t *log);
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static int ql_drvr_state(qla_host_t *ha, qla_driver_state_t *drvr_state);
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static uint32_t ql_drvr_state_size(qla_host_t *ha);
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static int ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td);
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static struct cdevsw qla_cdevsw = {
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.d_version = D_VERSION,
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.d_ioctl = ql_eioctl,
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.d_name = "qlcnic",
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};
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int
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ql_make_cdev(qla_host_t *ha)
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{
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ha->ioctl_dev = make_dev(&qla_cdevsw,
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ha->ifp->if_dunit,
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UID_ROOT,
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GID_WHEEL,
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0600,
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"%s",
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if_name(ha->ifp));
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if (ha->ioctl_dev == NULL)
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return (-1);
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ha->ioctl_dev->si_drv1 = ha;
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return (0);
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}
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void
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ql_del_cdev(qla_host_t *ha)
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{
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if (ha->ioctl_dev != NULL)
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destroy_dev(ha->ioctl_dev);
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return;
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}
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static int
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ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td)
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{
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qla_host_t *ha;
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int rval = 0;
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device_t pci_dev;
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struct ifnet *ifp;
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int count;
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q80_offchip_mem_val_t val;
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qla_rd_pci_ids_t *pci_ids;
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qla_rd_fw_dump_t *fw_dump;
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union {
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qla_reg_val_t *rv;
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qla_rd_flash_t *rdf;
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qla_wr_flash_t *wrf;
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qla_erase_flash_t *erf;
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qla_offchip_mem_val_t *mem;
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} u;
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if ((ha = (qla_host_t *)dev->si_drv1) == NULL)
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return ENXIO;
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pci_dev= ha->pci_dev;
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switch(cmd) {
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case QLA_RDWR_REG:
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u.rv = (qla_reg_val_t *)data;
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if (u.rv->direct) {
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if (u.rv->rd) {
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u.rv->val = READ_REG32(ha, u.rv->reg);
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} else {
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WRITE_REG32(ha, u.rv->reg, u.rv->val);
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}
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} else {
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if ((rval = ql_rdwr_indreg32(ha, u.rv->reg, &u.rv->val,
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u.rv->rd)))
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rval = ENXIO;
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}
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break;
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case QLA_RD_FLASH:
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if (!ha->hw.flags.fdt_valid) {
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rval = EIO;
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break;
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}
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u.rdf = (qla_rd_flash_t *)data;
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if ((rval = ql_rd_flash32(ha, u.rdf->off, &u.rdf->data)))
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rval = ENXIO;
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break;
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case QLA_WR_FLASH:
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ifp = ha->ifp;
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if (ifp == NULL) {
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rval = ENXIO;
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break;
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}
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if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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rval = ENXIO;
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break;
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}
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if (!ha->hw.flags.fdt_valid) {
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rval = EIO;
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break;
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}
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u.wrf = (qla_wr_flash_t *)data;
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if ((rval = ql_wr_flash_buffer(ha, u.wrf->off, u.wrf->size,
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u.wrf->buffer))) {
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printf("flash write failed[%d]\n", rval);
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rval = ENXIO;
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}
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break;
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case QLA_ERASE_FLASH:
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ifp = ha->ifp;
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if (ifp == NULL) {
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rval = ENXIO;
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break;
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}
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if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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rval = ENXIO;
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break;
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}
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if (!ha->hw.flags.fdt_valid) {
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rval = EIO;
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break;
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}
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u.erf = (qla_erase_flash_t *)data;
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if ((rval = ql_erase_flash(ha, u.erf->off,
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u.erf->size))) {
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printf("flash erase failed[%d]\n", rval);
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rval = ENXIO;
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}
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break;
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case QLA_RDWR_MS_MEM:
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u.mem = (qla_offchip_mem_val_t *)data;
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if ((rval = ql_rdwr_offchip_mem(ha, u.mem->off, &val,
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u.mem->rd)))
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rval = ENXIO;
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else {
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u.mem->data_lo = val.data_lo;
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u.mem->data_hi = val.data_hi;
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u.mem->data_ulo = val.data_ulo;
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u.mem->data_uhi = val.data_uhi;
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}
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break;
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case QLA_RD_FW_DUMP_SIZE:
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if (ha->hw.mdump_init == 0) {
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rval = EINVAL;
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break;
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}
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fw_dump = (qla_rd_fw_dump_t *)data;
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fw_dump->minidump_size = ha->hw.mdump_buffer_size +
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ha->hw.mdump_template_size;
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fw_dump->pci_func = ha->pci_func;
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break;
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case QLA_RD_FW_DUMP:
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if (ha->hw.mdump_init == 0) {
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device_printf(pci_dev, "%s: minidump not initialized\n", __func__);
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rval = EINVAL;
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break;
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}
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fw_dump = (qla_rd_fw_dump_t *)data;
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if ((fw_dump->minidump == NULL) ||
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(fw_dump->minidump_size != (ha->hw.mdump_buffer_size +
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ha->hw.mdump_template_size))) {
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device_printf(pci_dev,
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"%s: minidump buffer [%p] size = [%d, %d] invalid\n", __func__,
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fw_dump->minidump, fw_dump->minidump_size,
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(ha->hw.mdump_buffer_size + ha->hw.mdump_template_size));
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rval = EINVAL;
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break;
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}
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if ((ha->pci_func & 0x1)) {
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device_printf(pci_dev, "%s: mindump allowed only on Port0\n", __func__);
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rval = ENXIO;
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break;
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}
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fw_dump->saved = 1;
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if (ha->offline) {
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if (ha->enable_minidump)
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ql_minidump(ha);
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fw_dump->saved = 0;
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fw_dump->usec_ts = ha->hw.mdump_usec_ts;
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if (!ha->hw.mdump_done) {
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device_printf(pci_dev,
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"%s: port offline minidump failed\n", __func__);
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rval = ENXIO;
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break;
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}
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} else {
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#define QLA_LOCK_MDUMP_MS_TIMEOUT (QLA_LOCK_DEFAULT_MS_TIMEOUT * 5)
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if (QLA_LOCK(ha, __func__, QLA_LOCK_MDUMP_MS_TIMEOUT, 0) == 0) {
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if (!ha->hw.mdump_done) {
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fw_dump->saved = 0;
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QL_INITIATE_RECOVERY(ha);
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device_printf(pci_dev, "%s: recovery initiated "
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" to trigger minidump\n",
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__func__);
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}
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QLA_UNLOCK(ha, __func__);
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} else {
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device_printf(pci_dev, "%s: QLA_LOCK() failed0\n", __func__);
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rval = ENXIO;
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break;
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}
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#define QLNX_DUMP_WAIT_SECS 30
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count = QLNX_DUMP_WAIT_SECS * 1000;
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while (count) {
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if (ha->hw.mdump_done)
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break;
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qla_mdelay(__func__, 100);
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count -= 100;
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}
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if (!ha->hw.mdump_done) {
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device_printf(pci_dev,
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"%s: port not offline minidump failed\n", __func__);
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rval = ENXIO;
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break;
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}
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fw_dump->usec_ts = ha->hw.mdump_usec_ts;
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if (QLA_LOCK(ha, __func__, QLA_LOCK_MDUMP_MS_TIMEOUT, 0) == 0) {
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ha->hw.mdump_done = 0;
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QLA_UNLOCK(ha, __func__);
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} else {
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device_printf(pci_dev, "%s: QLA_LOCK() failed1\n", __func__);
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rval = ENXIO;
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break;
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}
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}
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if ((rval = copyout(ha->hw.mdump_template,
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fw_dump->minidump, ha->hw.mdump_template_size))) {
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device_printf(pci_dev, "%s: template copyout failed\n", __func__);
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rval = ENXIO;
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break;
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}
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if ((rval = copyout(ha->hw.mdump_buffer,
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((uint8_t *)fw_dump->minidump +
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ha->hw.mdump_template_size),
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ha->hw.mdump_buffer_size))) {
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device_printf(pci_dev, "%s: minidump copyout failed\n", __func__);
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rval = ENXIO;
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}
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break;
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case QLA_RD_DRVR_STATE:
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rval = ql_drvr_state(ha, (qla_driver_state_t *)data);
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break;
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case QLA_RD_SLOWPATH_LOG:
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rval = ql_slowpath_log(ha, (qla_sp_log_t *)data);
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break;
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case QLA_RD_PCI_IDS:
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pci_ids = (qla_rd_pci_ids_t *)data;
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pci_ids->ven_id = pci_get_vendor(pci_dev);
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pci_ids->dev_id = pci_get_device(pci_dev);
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pci_ids->subsys_ven_id = pci_get_subvendor(pci_dev);
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pci_ids->subsys_dev_id = pci_get_subdevice(pci_dev);
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pci_ids->rev_id = pci_read_config(pci_dev, PCIR_REVID, 1);
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break;
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default:
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break;
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}
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return rval;
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}
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static int
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ql_drvr_state(qla_host_t *ha, qla_driver_state_t *state)
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{
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int rval = 0;
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uint32_t drvr_state_size;
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drvr_state_size = ql_drvr_state_size(ha);
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if (state->buffer == NULL) {
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state->size = drvr_state_size;
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return (0);
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}
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if (state->size < drvr_state_size)
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return (ENXIO);
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if (ha->hw.drvr_state == NULL)
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return (ENOMEM);
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ql_capture_drvr_state(ha);
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rval = copyout(ha->hw.drvr_state, state->buffer, drvr_state_size);
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bzero(ha->hw.drvr_state, drvr_state_size);
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return (rval);
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}
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static uint32_t
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ql_drvr_state_size(qla_host_t *ha)
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{
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uint32_t drvr_state_size;
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uint32_t size;
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size = sizeof (qla_drvr_state_hdr_t);
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drvr_state_size = QL_ALIGN(size, 64);
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size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t));
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS * ha->hw.num_tx_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS * ha->hw.num_rds_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS *
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ha->hw.num_sds_rings;
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drvr_state_size += QL_ALIGN(size, 64);
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return (drvr_state_size);
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}
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static void
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ql_get_tx_state(qla_host_t *ha, qla_drvr_state_tx_t *tx_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_tx_rings; i++) {
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tx_state->base_p_addr = ha->hw.tx_cntxt[i].tx_ring_paddr;
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tx_state->cons_p_addr = ha->hw.tx_cntxt[i].tx_cons_paddr;
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tx_state->tx_prod_reg = ha->hw.tx_cntxt[i].tx_prod_reg;
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tx_state->tx_cntxt_id = ha->hw.tx_cntxt[i].tx_cntxt_id;
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tx_state->txr_free = ha->hw.tx_cntxt[i].txr_free;
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tx_state->txr_next = ha->hw.tx_cntxt[i].txr_next;
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tx_state->txr_comp = ha->hw.tx_cntxt[i].txr_comp;
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tx_state++;
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}
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return;
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}
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static void
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ql_get_rx_state(qla_host_t *ha, qla_drvr_state_rx_t *rx_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_rds_rings; i++) {
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rx_state->prod_std = ha->hw.rds[i].prod_std;
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rx_state->rx_next = ha->hw.rds[i].rx_next;
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rx_state++;
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}
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return;
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}
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static void
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ql_get_sds_state(qla_host_t *ha, qla_drvr_state_sds_t *sds_state)
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{
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int i;
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for (i = 0; i < ha->hw.num_sds_rings; i++) {
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sds_state->sdsr_next = ha->hw.sds[i].sdsr_next;
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sds_state->sds_consumer = ha->hw.sds[i].sds_consumer;
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sds_state++;
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}
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return;
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}
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void
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ql_capture_drvr_state(qla_host_t *ha)
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{
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uint8_t *state_buffer;
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uint8_t *ptr;
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qla_drvr_state_hdr_t *hdr;
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uint32_t size;
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int i;
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state_buffer = ha->hw.drvr_state;
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if (state_buffer == NULL)
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return;
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hdr = (qla_drvr_state_hdr_t *)state_buffer;
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hdr->saved = 0;
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if (hdr->drvr_version_major) {
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hdr->saved = 1;
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return;
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}
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hdr->usec_ts = qla_get_usec_timestamp();
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hdr->drvr_version_major = QLA_VERSION_MAJOR;
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hdr->drvr_version_minor = QLA_VERSION_MINOR;
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hdr->drvr_version_build = QLA_VERSION_BUILD;
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bcopy(ha->hw.mac_addr, hdr->mac_addr, ETHER_ADDR_LEN);
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hdr->link_speed = ha->hw.link_speed;
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hdr->cable_length = ha->hw.cable_length;
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hdr->cable_oui = ha->hw.cable_oui;
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hdr->link_up = ha->hw.link_up;
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hdr->module_type = ha->hw.module_type;
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hdr->link_faults = ha->hw.link_faults;
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hdr->rcv_intr_coalesce = ha->hw.rcv_intr_coalesce;
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hdr->xmt_intr_coalesce = ha->hw.xmt_intr_coalesce;
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|
|
|
size = sizeof (qla_drvr_state_hdr_t);
|
|
hdr->tx_state_offset = QL_ALIGN(size, 64);
|
|
|
|
ptr = state_buffer + hdr->tx_state_offset;
|
|
|
|
ql_get_tx_state(ha, (qla_drvr_state_tx_t *)ptr);
|
|
|
|
size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t));
|
|
hdr->rx_state_offset = hdr->tx_state_offset + QL_ALIGN(size, 64);
|
|
ptr = state_buffer + hdr->rx_state_offset;
|
|
|
|
ql_get_rx_state(ha, (qla_drvr_state_rx_t *)ptr);
|
|
|
|
size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t));
|
|
hdr->sds_state_offset = hdr->rx_state_offset + QL_ALIGN(size, 64);
|
|
ptr = state_buffer + hdr->sds_state_offset;
|
|
|
|
ql_get_sds_state(ha, (qla_drvr_state_sds_t *)ptr);
|
|
|
|
size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t));
|
|
hdr->txr_offset = hdr->sds_state_offset + QL_ALIGN(size, 64);
|
|
ptr = state_buffer + hdr->txr_offset;
|
|
|
|
hdr->num_tx_rings = ha->hw.num_tx_rings;
|
|
hdr->txr_size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS;
|
|
hdr->txr_entries = NUM_TX_DESCRIPTORS;
|
|
|
|
size = hdr->num_tx_rings * hdr->txr_size;
|
|
bcopy(ha->hw.dma_buf.tx_ring.dma_b, ptr, size);
|
|
|
|
hdr->rxr_offset = hdr->txr_offset + QL_ALIGN(size, 64);
|
|
ptr = state_buffer + hdr->rxr_offset;
|
|
|
|
hdr->rxr_size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS;
|
|
hdr->rxr_entries = NUM_RX_DESCRIPTORS;
|
|
hdr->num_rx_rings = ha->hw.num_rds_rings;
|
|
|
|
for (i = 0; i < ha->hw.num_rds_rings; i++) {
|
|
bcopy(ha->hw.dma_buf.rds_ring[i].dma_b, ptr, hdr->rxr_size);
|
|
ptr += hdr->rxr_size;
|
|
}
|
|
|
|
size = hdr->rxr_size * hdr->num_rx_rings;
|
|
hdr->sds_offset = hdr->rxr_offset + QL_ALIGN(size, 64);
|
|
hdr->sds_ring_size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS;
|
|
hdr->sds_entries = NUM_STATUS_DESCRIPTORS;
|
|
hdr->num_sds_rings = ha->hw.num_sds_rings;
|
|
|
|
ptr = state_buffer + hdr->sds_offset;
|
|
for (i = 0; i < ha->hw.num_sds_rings; i++) {
|
|
bcopy(ha->hw.dma_buf.sds_ring[i].dma_b, ptr, hdr->sds_ring_size);
|
|
ptr += hdr->sds_ring_size;
|
|
}
|
|
return;
|
|
}
|
|
|
|
void
|
|
ql_alloc_drvr_state_buffer(qla_host_t *ha)
|
|
{
|
|
uint32_t drvr_state_size;
|
|
|
|
drvr_state_size = ql_drvr_state_size(ha);
|
|
|
|
ha->hw.drvr_state = malloc(drvr_state_size, M_QLA83XXBUF, M_NOWAIT);
|
|
|
|
if (ha->hw.drvr_state != NULL)
|
|
bzero(ha->hw.drvr_state, drvr_state_size);
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
ql_free_drvr_state_buffer(qla_host_t *ha)
|
|
{
|
|
if (ha->hw.drvr_state != NULL)
|
|
free(ha->hw.drvr_state, M_QLA83XXBUF);
|
|
return;
|
|
}
|
|
|
|
void
|
|
ql_sp_log(qla_host_t *ha, uint16_t fmtstr_idx, uint16_t num_params,
|
|
uint32_t param0, uint32_t param1, uint32_t param2, uint32_t param3,
|
|
uint32_t param4)
|
|
{
|
|
qla_sp_log_entry_t *sp_e, *sp_log;
|
|
|
|
if (((sp_log = ha->hw.sp_log) == NULL) || ha->hw.sp_log_stop)
|
|
return;
|
|
|
|
mtx_lock(&ha->sp_log_lock);
|
|
|
|
sp_e = &sp_log[ha->hw.sp_log_index];
|
|
|
|
bzero(sp_e, sizeof (qla_sp_log_entry_t));
|
|
|
|
sp_e->fmtstr_idx = fmtstr_idx;
|
|
sp_e->num_params = num_params;
|
|
|
|
sp_e->usec_ts = qla_get_usec_timestamp();
|
|
|
|
sp_e->params[0] = param0;
|
|
sp_e->params[1] = param1;
|
|
sp_e->params[2] = param2;
|
|
sp_e->params[3] = param3;
|
|
sp_e->params[4] = param4;
|
|
|
|
ha->hw.sp_log_index = (ha->hw.sp_log_index + 1) & (NUM_LOG_ENTRIES - 1);
|
|
|
|
if (ha->hw.sp_log_num_entries < NUM_LOG_ENTRIES)
|
|
ha->hw.sp_log_num_entries++;
|
|
|
|
mtx_unlock(&ha->sp_log_lock);
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
ql_alloc_sp_log_buffer(qla_host_t *ha)
|
|
{
|
|
uint32_t size;
|
|
|
|
size = (sizeof(qla_sp_log_entry_t)) * NUM_LOG_ENTRIES;
|
|
|
|
ha->hw.sp_log = malloc(size, M_QLA83XXBUF, M_NOWAIT);
|
|
|
|
if (ha->hw.sp_log != NULL)
|
|
bzero(ha->hw.sp_log, size);
|
|
|
|
ha->hw.sp_log_index = 0;
|
|
ha->hw.sp_log_num_entries = 0;
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
ql_free_sp_log_buffer(qla_host_t *ha)
|
|
{
|
|
if (ha->hw.sp_log != NULL)
|
|
free(ha->hw.sp_log, M_QLA83XXBUF);
|
|
return;
|
|
}
|
|
|
|
static int
|
|
ql_slowpath_log(qla_host_t *ha, qla_sp_log_t *log)
|
|
{
|
|
int rval = 0;
|
|
uint32_t size;
|
|
|
|
if ((ha->hw.sp_log == NULL) || (log->buffer == NULL))
|
|
return (EINVAL);
|
|
|
|
size = (sizeof(qla_sp_log_entry_t) * NUM_LOG_ENTRIES);
|
|
|
|
mtx_lock(&ha->sp_log_lock);
|
|
|
|
rval = copyout(ha->hw.sp_log, log->buffer, size);
|
|
|
|
if (!rval) {
|
|
log->next_idx = ha->hw.sp_log_index;
|
|
log->num_entries = ha->hw.sp_log_num_entries;
|
|
}
|
|
device_printf(ha->pci_dev,
|
|
"%s: exit [rval = %d][%p, next_idx = %d, %d entries, %d bytes]\n",
|
|
__func__, rval, log->buffer, log->next_idx, log->num_entries, size);
|
|
mtx_unlock(&ha->sp_log_lock);
|
|
|
|
return (rval);
|
|
}
|
|
|