271 lines
7.4 KiB
C
271 lines
7.4 KiB
C
/*-
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* Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com)
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* Copyright (c) LAN Media Corporation 1998, 1999.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* From NetBSD: if_de.c,v 1.56.2.1 1997/10/27 02:13:25 thorpej Exp
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* $Id: if_lmc_common.c,v 1.12 1999/03/01 15:22:37 explorer Exp $
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*/
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/*
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* the dec chip has its own idea of what a receive error is, but we don't
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* want to use it, as it will get the crc error wrong when 16-bit
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* crcs are used. So, we only care about certain conditions.
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*/
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#ifndef TULIP_DSTS_RxMIIERR
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#define TULIP_DSTS_RxMIIERR 0x00000008
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#endif
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#define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
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static void
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lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits)
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{
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sc->lmc_gpio_io &= ~bits;
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LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
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}
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static void
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lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits)
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{
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sc->lmc_gpio_io |= bits;
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LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
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}
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static void
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lmc_led_on(lmc_softc_t * const sc, u_int32_t led)
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{
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sc->lmc_miireg16 &= ~led;
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lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
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}
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static void
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lmc_led_off(lmc_softc_t * const sc, u_int32_t led)
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{
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sc->lmc_miireg16 |= led;
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lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
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}
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static void
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lmc_reset(lmc_softc_t * const sc)
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{
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sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
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lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
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sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
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lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
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/*
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* make some of the GPIO pins be outputs
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*/
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lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
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/*
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* drive DP and RESET low to force configuration. This also forces
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* the transmitter clock to be internal, but we expect to reset
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* that later anyway.
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*/
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sc->lmc_gpio &= ~(LMC_GEP_DP | LMC_GEP_RESET);
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LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
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/*
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* hold for more than 10 microseconds
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*/
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DELAY(50);
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/*
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* stop driving Xilinx-related signals
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*/
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lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
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/*
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* busy wait for the chip to reset
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*/
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while ((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0)
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;
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/*
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* Call media specific init routine
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*/
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sc->lmc_media->init(sc);
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}
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static void
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lmc_dec_reset(lmc_softc_t * const sc)
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{
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#ifndef __linux__
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lmc_ringinfo_t *ri;
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tulip_desc_t *di;
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#endif
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u_int32_t val;
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/*
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* disable all interrupts
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*/
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sc->lmc_intrmask = 0;
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LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
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/*
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* we are, obviously, down.
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*/
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#ifndef __linux__
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sc->lmc_flags &= ~(LMC_IFUP | LMC_MODEMOK);
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DP(("lmc_dec_reset\n"));
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#endif
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/*
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* Reset the chip with a software reset command.
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* Wait 10 microseconds (actually 50 PCI cycles but at
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* 33MHz that comes to two microseconds but wait a
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* bit longer anyways)
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*/
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LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
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DELAY(10);
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sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
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/*
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* We want:
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* no ethernet address in frames we write
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* disable padding (txdesc, padding disable)
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* ignore runt frames (rdes0 bit 15)
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* no receiver watchdog or transmitter jabber timer
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* (csr15 bit 0,14 == 1)
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* if using 16-bit CRC, turn off CRC (trans desc, crc disable)
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*/
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#ifndef TULIP_CMD_RECEIVEALL
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#define TULIP_CMD_RECEIVEALL 0x40000000L
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#endif
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sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
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| TULIP_CMD_FULLDUPLEX
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| TULIP_CMD_PASSBADPKT
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| TULIP_CMD_NOHEARTBEAT
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| TULIP_CMD_PORTSELECT
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| TULIP_CMD_RECEIVEALL
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| TULIP_CMD_MUSTBEONE
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);
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sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
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| TULIP_CMD_THRESHOLDCTL
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| TULIP_CMD_STOREFWD
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| TULIP_CMD_TXTHRSHLDCTL
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);
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LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
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/*
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* disable receiver watchdog and transmit jabber
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*/
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val = LMC_CSR_READ(sc, csr_sia_general);
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val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
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LMC_CSR_WRITE(sc, csr_sia_general, val);
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/*
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* turn off those LEDs...
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*/
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sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
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lmc_led_on(sc, LMC_MII16_LED0);
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#ifndef __linux__
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/*
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* reprogram the tx desc, rx desc, and PCI bus options
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*/
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LMC_CSR_WRITE(sc, csr_txlist,
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LMC_KVATOPHYS(sc, &sc->lmc_txinfo.ri_first[0]));
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LMC_CSR_WRITE(sc, csr_rxlist,
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LMC_KVATOPHYS(sc, &sc->lmc_rxinfo.ri_first[0]));
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LMC_CSR_WRITE(sc, csr_busmode,
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(1 << (LMC_BURSTSIZE(sc->lmc_unit) + 8))
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|TULIP_BUSMODE_CACHE_ALIGN8
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|TULIP_BUSMODE_READMULTIPLE
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|(BYTE_ORDER != LITTLE_ENDIAN ? TULIP_BUSMODE_BIGENDIAN : 0));
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sc->lmc_txq.ifq_maxlen = LMC_TXDESCS;
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/*
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* Free all the mbufs that were on the transmit ring.
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*/
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for (;;) {
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struct mbuf *m;
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_IF_DEQUEUE(&sc->lmc_txq, m);
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if (m == NULL)
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break;
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m_freem(m);
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}
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/*
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* reset descriptor state and reclaim all descriptors.
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*/
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ri = &sc->lmc_txinfo;
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ri->ri_nextin = ri->ri_nextout = ri->ri_first;
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ri->ri_free = ri->ri_max;
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for (di = ri->ri_first; di < ri->ri_last; di++)
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di->d_status = 0;
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/*
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* We need to collect all the mbufs were on the
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* receive ring before we reinit it either to put
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* them back on or to know if we have to allocate
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* more.
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*/
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ri = &sc->lmc_rxinfo;
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ri->ri_nextin = ri->ri_nextout = ri->ri_first;
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ri->ri_free = ri->ri_max;
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for (di = ri->ri_first; di < ri->ri_last; di++) {
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di->d_status = 0;
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di->d_length1 = 0; di->d_addr1 = 0;
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di->d_length2 = 0; di->d_addr2 = 0;
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}
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for (;;) {
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struct mbuf *m;
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_IF_DEQUEUE(&sc->lmc_rxq, m);
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if (m == NULL)
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break;
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m_freem(m);
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}
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#endif
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}
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static void
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lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base,
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size_t csr_size)
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{
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sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
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sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
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sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
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sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
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sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
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sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
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sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
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sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
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sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
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sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
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sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
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sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
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sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
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sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
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sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
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sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
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}
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