ba81aae287
(and accurate). T4 and later have an extra bit for page shift so the maximum page size is 8TB (shift of 12 + 31) instead of 128MB (12 + 15). This saves space in the chip's PBL (physical buffer list) when registering very large memory regions. MFC after: 3 days Sponsored by: Chelsio Communications |
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.. | ||
common | ||
cxgbei | ||
firmware | ||
iw_cxgbe | ||
tom | ||
adapter.h | ||
if_cc.c | ||
if_ccv.c | ||
if_cxl.c | ||
if_cxlv.c | ||
offload.h | ||
osdep.h | ||
t4_if.m | ||
t4_ioctl.h | ||
t4_iov.c | ||
t4_l2t.c | ||
t4_l2t.h | ||
t4_main.c | ||
t4_mp_ring.c | ||
t4_mp_ring.h | ||
t4_netmap.c | ||
t4_sge.c | ||
t4_tracer.c | ||
t4_vf.c |