562246dff8
specially aml8726-m6 and aml8726-m8b SoC based devices. aml8726-m6 SoC exist in devices such as Visson ATV-102. Hardkernel ODROID-C1 board has aml8726-m8b SoC. The following support is included: Basic machdep code SMP Interrupt controller Clock control driver (aka gate) Pinctrl Timer Real time clock UART GPIO I2C SD controller SDXC controller USB Watchdog Random number generator PLL / Clock frequency measurement Frame buffer Submitted by: John Wehle Approved by: stas (mentor)
138 lines
5.2 KiB
C
138 lines
5.2 KiB
C
/*-
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* Copyright 2013-2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM_AMLOGIC_AML8726_MMC_H
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#define _ARM_AMLOGIC_AML8726_MMC_H
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#define AML_MMC_ALIGN_DMA 4
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#define AML_MMC_MAX_DMA 4096
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/*
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* Timeouts are in milliseconds
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*
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* Read and write are per section 4.6.2 of the:
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*
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* SD Specifications Part 1
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* Physicaly Layer Simplified Specification
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* Version 4.10
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*/
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#define AML_MMC_CMD_TIMEOUT 50
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#define AML_MMC_READ_TIMEOUT 100
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#define AML_MMC_WRITE_TIMEOUT 500
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#define AML_MMC_MAX_TIMEOUT 5000
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/*
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* Internally the timeout is implemented by counting clock cycles.
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*
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* Since the hardware implements timeouts by counting cycles
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* the minimum read / write timeout (assuming the minimum
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* conversion factor of 1 cycle per usec) is:
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*
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* (8 bits * 512 bytes per block + 16 bits CRC) = 4112 usec
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*/
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#if ((AML_MMC_READ_TIMEOUT * 1000) < 4112 || \
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(AML_MMC_WRITE_TIMEOUT * 1000) < 4112)
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#error "Single block timeout is smaller than supported"
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#endif
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#define AML_MMC_CMD_ARGUMENT_REG 0
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#define AML_MMC_CMD_SEND_REG 4
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#define AML_MMC_CMD_REP_PKG_CNT_MASK (0xffU << 24)
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#define AML_MMC_CMD_REP_PKG_CNT_SHIFT 24
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#define AML_MMC_CMD_CMD_HAS_DATA (1 << 20)
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#define AML_MMC_CMD_CHECK_DAT0_BUSY (1 << 19)
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#define AML_MMC_CMD_RESP_CRC7_FROM_8 (1 << 18)
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#define AML_MMC_CMD_RESP_HAS_DATA (1 << 17)
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#define AML_MMC_CMD_RESP_NO_CRC7 (1 << 16)
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#define AML_MMC_CMD_RESP_BITS_MASK (0xff << 8)
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#define AML_MMC_CMD_RESP_BITS_SHIFT 8
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#define AML_MMC_CMD_START_BIT (0 << 7)
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#define AML_MMC_CMD_TRANS_BIT_HOST (1 << 6)
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#define AML_MMC_CMD_INDEX_MASK 0x3f
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#define AML_MMC_CMD_INDEX_SHIFT 0
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#define AML_MMC_CONFIG_REG 8
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#define AML_MMC_CONFIG_WR_CRC_STAT_MASK (7U << 29)
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#define AML_MMC_CONFIG_WR_CRC_STAT_SHIFT 29
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#define AML_MMC_CONFIG_WR_DELAY_MASK (0x3f << 23)
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#define AML_MMC_CONFIG_WR_DELAY_SHIFT 23
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#define AML_MMC_CONFIG_DMA_ENDIAN_MASK (3 << 21)
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#define AML_MMC_CONFIG_DMA_ENDIAN_NC (0 << 21)
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#define AML_MMC_CONFIG_DMA_ENDIAN_SB (1 << 21)
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#define AML_MMC_CONFIG_DMA_ENDIAN_SW (2 << 21)
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#define AML_MMC_CONFIG_DMA_ENDIAN_SBW (3 << 21)
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#define AML_MMC_CONFIG_BUS_WIDTH_MASK (1 << 20)
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#define AML_MMC_CONFIG_BUS_WIDTH_1 (0 << 20)
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#define AML_MMC_CONFIG_BUS_WIDTH_4 (1 << 20)
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#define AML_MMC_CONFIG_DATA_NEG_EDGE (1 << 19)
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#define AML_MMC_CONFIG_DONT_DELAY_DATA (1 << 18)
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#define AML_MMC_CONFIG_CMD_ARG_BITS_MASK (0x3f << 12)
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#define AML_MMC_CONFIG_CMD_ARG_BITS_SHIFT 12
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#define AML_MMC_CONFIG_CMD_POS_EDGE (1 << 11)
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#define AML_MMC_CONFIG_CMD_NO_CRC (1 << 10)
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#define AML_MMC_CONFIG_CMD_CLK_DIV_MASK 0x3ff
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#define AML_MMC_CONFIG_CMD_CLK_DIV_SHIFT 0
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#define AML_MMC_IRQ_STATUS_REG 12
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#define AML_MMC_IRQ_STATUS_TIMER_CNT_MASK (0x1fffU << 19)
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#define AML_MMC_IRQ_STATUS_TIMER_CNT_SHIFT 19
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#define AML_MMC_IRQ_STATUS_TIMER_EN (1 << 18)
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#define AML_MMC_IRQ_STATUS_TIMEOUT_IRQ (1 << 16)
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#define AML_MMC_IRQ_STATUS_CMD_DONE_IRQ (1 << 9)
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#define AML_MMC_IRQ_STATUS_WR_CRC16_OK (1 << 7)
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#define AML_MMC_IRQ_STATUS_RD_CRC16_OK (1 << 6)
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#define AML_MMC_IRQ_STATUS_RESP_CRC7_OK (1 << 5)
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#define AML_MMC_IRQ_STATUS_CMD_BUSY (1 << 4)
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#define AML_MMC_IRQ_STATUS_CLEAR_IRQ 0x10700
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#define AML_MMC_IRQ_CONFIG_REG 16
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#define AML_MMC_IRQ_CONFIG_SOFT_RESET (1 << 15)
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#define AML_MMC_IRQ_CONFIG_CMD_DONE_EN (1 << 4)
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#define AML_MMC_MULT_CONFIG_REG 20
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#define AML_MMC_MULT_CONFIG_RESP_INDEX_MASK (0xf << 12)
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#define AML_MMC_MULT_CONFIG_RESP_INDEX_SHIFT 12
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#define AML_MMC_MULT_CONFIG_RESP_READOUT_EN (1 << 8)
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#define AML_MMC_MULT_CONFIG_STREAM_8_MODE (1 << 5)
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#define AML_MMC_MULT_CONFIG_STREAM_EN (1 << 4)
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#define AML_MMC_MULT_CONFIG_PORT_MASK 3
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#define AML_MMC_MULT_CONFIG_PORT_A 0
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#define AML_MMC_MULT_CONFIG_PORT_B 1
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#define AML_MMC_MULT_CONFIG_PORT_C 2
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#define AML_MMC_DMA_ADDR_REG 24
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#define AML_MMC_EXTENSION_REG 28
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#define AML_MMC_EXTENSION_NO_CRC16 (1 << 30)
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#define AML_MMC_EXTENSION_PKT_SIZE_MASK (0x3fff << 16)
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#define AML_MMC_EXTENSION_PKT_SIZE_SHIFT 16
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#endif /* _ARM_AMLOGIC_AML8726_MMC_H */
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