2c66cccab7
the kernel on amd64. Fill and read segment registers for mcontext and signals. Handle traps caused by restoration of the invalidated selectors. Implement user-mode creation and manipulation of the process-specific LDT descriptors for amd64, see sysarch(2). Implement support for TSS i/o port access permission bitmap for amd64. Context-switch LDT and TSS. Do not save and restore segment registers on the context switch, that is handled by kernel enter/leave trampolines now. Remove segment restore code from the signal trampolines for freebsd/amd64, freebsd/ia32 and linux/i386 for the same reason. Implement amd64-specific compat shims for sysarch. Linuxolator (temporary ?) switched to use gsbase for thread_area pointer. TODO: Currently, gdb is not adapted to show segment registers from struct reg. Also, no machine-depended ptrace command is added to set segment registers for debugged process. In collaboration with: pho Discussed with: peter Reviewed by: jhb Linuxolator tested by: dchagin
232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
/*-
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* Copyright (c) 2005 Peter Wemm
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_compat.h"
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#include <sys/param.h>
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#include <sys/exec.h>
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#include <sys/fcntl.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/mman.h>
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#include <sys/namei.h>
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#include <sys/pioctl.h>
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#include <sys/proc.h>
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#include <sys/procfs.h>
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#include <sys/resourcevar.h>
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#include <sys/systm.h>
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#include <sys/signalvar.h>
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#include <sys/stat.h>
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#include <sys/sx.h>
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#include <sys/syscall.h>
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#include <sys/sysctl.h>
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#include <sys/sysent.h>
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#include <sys/vnode.h>
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#include <vm/vm.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <vm/vm_map.h>
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#include <vm/vm_object.h>
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#include <vm/vm_extern.h>
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#include <compat/freebsd32/freebsd32_util.h>
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#include <compat/freebsd32/freebsd32_proto.h>
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#include <machine/fpu.h>
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#include <compat/ia32/ia32_reg.h>
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#include <machine/psl.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#include <machine/frame.h>
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#include <machine/md_var.h>
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#include <machine/pcb.h>
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#include <machine/cpufunc.h>
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#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
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#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
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int
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fill_regs32(struct thread *td, struct reg32 *regs)
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{
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struct pcb *pcb;
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struct trapframe *tp;
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tp = td->td_frame;
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pcb = td->td_pcb;
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if (tp->tf_flags & TF_HASSEGS) {
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regs->r_gs = tp->tf_gs;
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regs->r_fs = tp->tf_fs;
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regs->r_es = tp->tf_es;
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regs->r_ds = tp->tf_ds;
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} else {
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regs->r_gs = _ugssel;
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regs->r_fs = _ufssel;
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regs->r_es = _udatasel;
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regs->r_ds = _udatasel;
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}
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regs->r_edi = tp->tf_rdi;
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regs->r_esi = tp->tf_rsi;
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regs->r_ebp = tp->tf_rbp;
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regs->r_ebx = tp->tf_rbx;
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regs->r_edx = tp->tf_rdx;
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regs->r_ecx = tp->tf_rcx;
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regs->r_eax = tp->tf_rax;
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regs->r_eip = tp->tf_rip;
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regs->r_cs = tp->tf_cs;
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regs->r_eflags = tp->tf_rflags;
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regs->r_esp = tp->tf_rsp;
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regs->r_ss = tp->tf_ss;
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return (0);
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}
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int
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set_regs32(struct thread *td, struct reg32 *regs)
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{
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struct pcb *pcb;
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struct trapframe *tp;
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tp = td->td_frame;
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if (!EFL_SECURE(regs->r_eflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs))
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return (EINVAL);
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pcb = td->td_pcb;
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tp->tf_gs = regs->r_gs;
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tp->tf_fs = regs->r_fs;
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tp->tf_es = regs->r_es;
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tp->tf_ds = regs->r_ds;
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tp->tf_flags = TF_HASSEGS;
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tp->tf_rdi = regs->r_edi;
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tp->tf_rsi = regs->r_esi;
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tp->tf_rbp = regs->r_ebp;
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tp->tf_rbx = regs->r_ebx;
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tp->tf_rdx = regs->r_edx;
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tp->tf_rcx = regs->r_ecx;
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tp->tf_rax = regs->r_eax;
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tp->tf_rip = regs->r_eip;
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tp->tf_cs = regs->r_cs;
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tp->tf_rflags = regs->r_eflags;
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tp->tf_rsp = regs->r_esp;
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tp->tf_ss = regs->r_ss;
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return (0);
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}
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int
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fill_fpregs32(struct thread *td, struct fpreg32 *regs)
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{
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struct save87 *sv_87 = (struct save87 *)regs;
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struct env87 *penv_87 = &sv_87->sv_env;
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struct savefpu *sv_fpu = &td->td_pcb->pcb_save;
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struct envxmm *penv_xmm = &sv_fpu->sv_env;
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int i;
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bzero(regs, sizeof(*regs));
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/* FPU control/status */
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penv_87->en_cw = penv_xmm->en_cw;
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penv_87->en_sw = penv_xmm->en_sw;
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penv_87->en_tw = penv_xmm->en_tw;
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/*
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* XXX for en_fip/fcs/foo/fos, check if the fxsave format
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* uses the old-style layout for 32 bit user apps. If so,
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* read the ip and operand segment registers from there.
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* For now, use the process's %cs/%ds.
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*/
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penv_87->en_fip = penv_xmm->en_rip;
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penv_87->en_fcs = td->td_frame->tf_cs;
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penv_87->en_opcode = penv_xmm->en_opcode;
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penv_87->en_foo = penv_xmm->en_rdp;
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/* Entry into the kernel always sets TF_HASSEGS */
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penv_87->en_fos = td->td_frame->tf_ds;
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/* FPU registers */
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for (i = 0; i < 8; ++i)
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sv_87->sv_ac[i] = sv_fpu->sv_fp[i].fp_acc;
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return (0);
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}
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int
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set_fpregs32(struct thread *td, struct fpreg32 *regs)
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{
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struct save87 *sv_87 = (struct save87 *)regs;
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struct env87 *penv_87 = &sv_87->sv_env;
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struct savefpu *sv_fpu = &td->td_pcb->pcb_save;
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struct envxmm *penv_xmm = &sv_fpu->sv_env;
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int i;
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/* FPU control/status */
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penv_xmm->en_cw = penv_87->en_cw;
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penv_xmm->en_sw = penv_87->en_sw;
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penv_xmm->en_tw = penv_87->en_tw;
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penv_xmm->en_rip = penv_87->en_fip;
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/* penv_87->en_fcs and en_fos ignored, see above */
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penv_xmm->en_opcode = penv_87->en_opcode;
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penv_xmm->en_rdp = penv_87->en_foo;
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/* FPU registers */
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for (i = 0; i < 8; ++i)
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sv_fpu->sv_fp[i].fp_acc = sv_87->sv_ac[i];
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for (i = 8; i < 16; ++i)
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bzero(&sv_fpu->sv_fp[i].fp_acc, sizeof(sv_fpu->sv_fp[i].fp_acc));
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return (0);
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}
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int
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fill_dbregs32(struct thread *td, struct dbreg32 *regs)
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{
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struct dbreg dr;
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int err, i;
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err = fill_dbregs(td, &dr);
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for (i = 0; i < 8; i++)
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regs->dr[i] = dr.dr[i];
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for (i = 8; i < 16; i++)
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regs->dr[i] = 0;
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return (err);
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}
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int
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set_dbregs32(struct thread *td, struct dbreg32 *regs)
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{
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struct dbreg dr;
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int i;
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for (i = 0; i < 8; i++)
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dr.dr[i] = regs->dr[i];
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for (i = 8; i < 16; i++)
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dr.dr[i] = 0;
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return (set_dbregs(td, &dr));
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}
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