718cf2ccb9
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362 lines
14 KiB
C
362 lines
14 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef XGE_HAL_FIFO_H
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#define XGE_HAL_FIFO_H
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#include <dev/nxge/include/xgehal-channel.h>
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#include <dev/nxge/include/xgehal-config.h>
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#include <dev/nxge/include/xgehal-mm.h>
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__EXTERN_BEGIN_DECLS
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/* HW fifo configuration */
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#define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65
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#define XGE_HAL_FIFO_MAX_WRR 5
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#define XGE_HAL_FIFO_MAX_PARTITION 4
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#define XGE_HAL_FIFO_MAX_WRR_STATE 36
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#define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000
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/* HW FIFO Weight Calender */
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#define XGE_HAL_FIFO_WRR_0 0x0706050407030602ULL
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#define XGE_HAL_FIFO_WRR_1 0x0507040601070503ULL
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#define XGE_HAL_FIFO_WRR_2 0x0604070205060700ULL
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#define XGE_HAL_FIFO_WRR_3 0x0403060705010207ULL
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#define XGE_HAL_FIFO_WRR_4 0x0604050300000000ULL
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/*
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* xge_hal_fifo_hw_pair_t
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*
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* Represent a single fifo in the BAR1 memory space.
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*/
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typedef struct {
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u64 txdl_pointer; /* offset 0x0 */
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u64 reserved[2];
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u64 list_control; /* offset 0x18 */
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#define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
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#define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14)
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#define XGE_HAL_TX_FIFO_LAST_LIST BIT(15)
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#define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
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#define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23)
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#define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2)
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} xge_hal_fifo_hw_pair_t;
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/* Bad TxDL transfer codes */
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#define XGE_HAL_TXD_T_CODE_OK 0x0
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#define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1
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#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2
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#define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3
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#define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5
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#define XGE_HAL_TXD_T_CODE_PARITY 0x7
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#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA
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#define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF
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/**
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* struct xge_hal_fifo_txd_t - TxD.
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* @control_1: Control_1.
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* @control_2: Control_2.
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* @buffer_pointer: Buffer_Address.
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* @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe
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* descriptor prior to posting the latter on the channel
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* via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post().
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* The %host_control is returned as is to the ULD with each
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* completed descriptor.
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*
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* Transmit descriptor (TxD).Fifo descriptor contains configured number
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* (list) of TxDs. * For more details please refer to Xframe User Guide,
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* Section 5.4.2 "Transmit Descriptor (TxD) Format".
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*/
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typedef struct xge_hal_fifo_txd_t {
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u64 control_1;
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#define XGE_HAL_TXD_LIST_OWN_XENA BIT(7)
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#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
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#define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48)
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#define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48))
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#define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23))
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#define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22)
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#define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23)
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#define XGE_HAL_TXD_NO_LSO 0
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#define XGE_HAL_TXD_UDF_COF 1
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#define XGE_HAL_TXD_TCP_LSO 2
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#define XGE_HAL_TXD_UDP_LSO 3
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#define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2)
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#define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
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#define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
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#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
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u64 control_2;
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#define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
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#define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5)
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#define XGE_HAL_TXD_TX_CKO_TCP_EN BIT(6)
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#define XGE_HAL_TXD_TX_CKO_UDP_EN BIT(7)
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#define XGE_HAL_TXD_VLAN_ENABLE BIT(15)
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#define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16)
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#define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6)
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#define XGE_HAL_TXD_INT_TYPE_PER_LIST BIT(47)
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#define XGE_HAL_TXD_INT_TYPE_UTILZ BIT(46)
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#define XGE_HAL_TXD_SET_MARKER vBIT(0x6,0,4)
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u64 buffer_pointer;
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u64 host_control;
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} xge_hal_fifo_txd_t;
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typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t;
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/**
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* struct xge_hal_fifo_t - Fifo channel.
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* @channel: Channel "base" of this fifo, the common part of all HAL
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* channels.
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* @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs.
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* Note that for Xena the serialization is done across all device
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* fifos.
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* @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the
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* Xframe hardware (for details see Xframe user guide).
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* @config: Fifo configuration, part of device configuration
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* (see xge_hal_device_config_t{}).
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* @no_snoop_bits: See xge_hal_fifo_config_t{}.
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* @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
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* on TxDL please refer to Xframe UG.
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* @interrupt_type: FIXME: to-be-defined.
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* @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
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* per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t).
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* @priv_size: Per-Tx descriptor space reserved for upper-layer driver
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* usage.
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* @mempool: Memory pool, from which descriptors get allocated.
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* @align_size: TBD
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*
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* Fifo channel.
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* Note: The structure is cache line aligned.
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*/
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typedef struct xge_hal_fifo_t {
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xge_hal_channel_t channel;
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spinlock_t *post_lock_ptr;
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xge_hal_fifo_hw_pair_t *hw_pair;
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xge_hal_fifo_config_t *config;
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int no_snoop_bits;
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int txdl_per_memblock;
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u64 interrupt_type;
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int txdl_size;
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int priv_size;
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xge_hal_mempool_t *mempool;
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int align_size;
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} __xge_os_attr_cacheline_aligned xge_hal_fifo_t;
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/**
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* struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private
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* data.
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* @dma_addr: DMA (mapped) address of _this_ descriptor.
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* @dma_handle: DMA handle used to map the descriptor onto device.
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* @dma_offset: Descriptor's offset in the memory block. HAL allocates
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* descriptors in memory blocks (see
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* xge_hal_fifo_config_t{})
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* Each memblock is a contiguous block of DMA-able memory.
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* @frags: Total number of fragments (that is, contiguous data buffers)
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* carried by this TxDL.
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* @align_vaddr_start: (TODO).
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* @align_vaddr: Virtual address of the per-TxDL area in memory used for
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* alignement. Used to place one or more mis-aligned fragments
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* (the maximum defined by configration variable
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* @max_aligned_frags).
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* @align_dma_addr: DMA address translated from the @align_vaddr.
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* @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
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* @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
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* @align_dma_offset: The current offset into the @align_vaddr area.
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* Grows while filling the descriptor, gets reset.
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* @align_used_frags: (TODO).
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* @alloc_frags: Total number of fragments allocated.
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* @dang_frags: Number of fragments kept from release until this TxDL is freed.
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* @bytes_sent: TODO
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* @unused: TODO
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* @dang_txdl: (TODO).
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* @next_txdl_priv: (TODO).
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* @first_txdp: (TODO).
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* @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL
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* is freed.
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* @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
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* TxDL list.
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* @dtrh: Corresponding dtrh to this TxDL.
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* @memblock: Pointer to the TxDL memory block or memory page.
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* on the next send operation.
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* @dma_object: DMA address and handle of the memory block that contains
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* the descriptor. This member is used only in the "checked"
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* version of the HAL (to enforce certain assertions);
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* otherwise it gets compiled out.
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* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
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*
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* Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
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* information associated with the descriptor. Note that ULD can ask HAL
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* to allocate additional per-descriptor space for its own (ULD-specific)
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* purposes.
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*
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* See also: xge_hal_ring_rxd_priv_t{}.
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*/
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typedef struct xge_hal_fifo_txdl_priv_t {
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dma_addr_t dma_addr;
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pci_dma_h dma_handle;
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ptrdiff_t dma_offset;
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int frags;
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char *align_vaddr_start;
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char *align_vaddr;
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dma_addr_t align_dma_addr;
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pci_dma_h align_dma_handle;
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pci_dma_acc_h align_dma_acch;
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ptrdiff_t align_dma_offset;
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int align_used_frags;
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int alloc_frags;
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int dang_frags;
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unsigned int bytes_sent;
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int unused;
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xge_hal_fifo_txd_t *dang_txdl;
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struct xge_hal_fifo_txdl_priv_t *next_txdl_priv;
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xge_hal_fifo_txd_t *first_txdp;
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void *memblock;
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#ifdef XGE_DEBUG_ASSERT
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xge_hal_mempool_dma_t *dma_object;
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#endif
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#ifdef XGE_OS_MEMORY_CHECK
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int allocated;
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#endif
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} xge_hal_fifo_txdl_priv_t;
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/**
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* xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated
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* for the fifo.
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* @channelh: Channel handle.
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*/
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static inline int
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xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh)
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{
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return ((xge_hal_fifo_t *)channelh)->config->max_frags;
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}
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/* ========================= FIFO PRIVATE API ============================= */
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xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh,
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xge_hal_channel_attr_t *attr);
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void __hal_fifo_close(xge_hal_channel_h channelh);
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void __hal_fifo_hw_initialize(xge_hal_device_h hldev);
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xge_hal_status_e
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__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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void
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__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO)
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#define __HAL_STATIC_FIFO
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#define __HAL_INLINE_FIFO
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t*
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__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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u64 ctrl_1);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh,
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xge_hal_fifo_txd_t *txdp, int txdl_count);
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/* ========================= FIFO PUBLIC API ============================== */
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
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const int frags);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void*
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xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO int
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xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size,
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xge_hal_dtr_h dtr_sp);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num,
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xge_hal_dtr_h dtrs[]);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
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u8 *t_code);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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int frag_idx, dma_addr_t dma_pointer, int size);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh,
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xge_hal_dtr_h dtrh, int frag_idx, void *vaddr,
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dma_addr_t dma_pointer, int size, int misaligned_size);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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void *vaddr, int size);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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int frag_idx);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag);
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh);
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#else /* XGE_FASTPATH_EXTERN */
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#define __HAL_STATIC_FIFO static
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#define __HAL_INLINE_FIFO inline
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#include <dev/nxge/xgehal/xgehal-fifo-fp.c>
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#endif /* XGE_FASTPATH_INLINE */
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__EXTERN_END_DECLS
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#endif /* XGE_HAL_FIFO_H */
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