6031c68de4
layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks
341 lines
11 KiB
C
341 lines
11 KiB
C
/*-
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* Copyright (c) 2003 Peter Wemm.
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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/*
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* Page-directory and page-table entries follow this format, with a few
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define PG_V 0x001 /* P Valid */
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#define PG_RW 0x002 /* R/W Read/Write */
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#define PG_U 0x004 /* U/S User/Supervisor */
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#define PG_NC_PWT 0x008 /* PWT Write through */
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#define PG_NC_PCD 0x010 /* PCD Cache disable */
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#define PG_A 0x020 /* A Accessed */
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#define PG_M 0x040 /* D Dirty */
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#define PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
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#define PG_PTE_PAT 0x080 /* PAT PAT index */
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#define PG_G 0x100 /* G Global */
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#define PG_AVAIL1 0x200 /* / Available for system */
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#define PG_AVAIL2 0x400 /* < programmers use */
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#define PG_AVAIL3 0x800 /* \ */
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#define PG_PDE_PAT 0x1000 /* PAT PAT index */
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#define PG_NX (1ul<<63) /* No-execute */
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/* Our various interpretations of the above */
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#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */
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#define PG_MANAGED PG_AVAIL2
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#define PG_FRAME (0x000ffffffffff000ul)
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#define PG_PS_FRAME (0x000fffffffe00000ul)
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#define PG_PROT (PG_RW|PG_U) /* all protection bits . */
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#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */
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/* Page level cache control fields used to determine the PAT type */
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#define PG_PDE_CACHE (PG_PDE_PAT | PG_NC_PWT | PG_NC_PCD)
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#define PG_PTE_CACHE (PG_PTE_PAT | PG_NC_PWT | PG_NC_PCD)
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/*
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* Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
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* (PTE) page mappings have identical settings for the following fields:
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*/
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#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_PAT | \
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PG_M | PG_A | PG_NC_PCD | PG_NC_PWT | PG_U | PG_RW | PG_V)
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
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#define PGEX_I 0x10 /* during an instruction fetch */
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/*
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* Pte related macros. This is complicated by having to deal with
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* the sign extension of the 48th bit.
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*/
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#define KVADDR(l4, l3, l2, l1) ( \
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((unsigned long)-1 << 47) | \
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((unsigned long)(l4) << PML4SHIFT) | \
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((unsigned long)(l3) << PDPSHIFT) | \
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((unsigned long)(l2) << PDRSHIFT) | \
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((unsigned long)(l1) << PAGE_SHIFT))
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#define UVADDR(l4, l3, l2, l1) ( \
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((unsigned long)(l4) << PML4SHIFT) | \
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((unsigned long)(l3) << PDPSHIFT) | \
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((unsigned long)(l2) << PDRSHIFT) | \
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((unsigned long)(l1) << PAGE_SHIFT))
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/* Initial number of kernel page tables. */
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#ifndef NKPT
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#define NKPT 32
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#endif
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#define NKPML4E 1 /* number of kernel PML4 slots */
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#define NKPDPE howmany(NKPT, NPDEPG)/* number of kernel PDP slots */
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#define NUPML4E (NPML4EPG/2) /* number of userland PML4 pages */
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#define NUPDPE (NUPML4E*NPDPEPG)/* number of userland PDP pages */
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#define NUPDE (NUPDPE*NPDEPG) /* number of userland PD entries */
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/*
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* NDMPML4E is the number of PML4 entries that are used to implement the
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* direct map. It must be a power of two.
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*/
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#define NDMPML4E 2
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/*
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* The *PDI values control the layout of virtual memory. The starting address
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* of the direct map, which is controlled by DMPML4I, must be a multiple of
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* its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
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*/
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#define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */
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#define KPML4I (NPML4EPG-1) /* Top 512GB for KVM */
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#define DMPML4I rounddown(KPML4I - NDMPML4E, NDMPML4E) /* Below KVM */
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#define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
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/*
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* XXX doesn't really belong here I guess...
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*/
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#define ISA_HOLE_START 0xa0000
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#define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
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#ifndef LOCORE
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#include <sys/queue.h>
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#include <sys/_cpuset.h>
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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typedef u_int64_t pd_entry_t;
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typedef u_int64_t pt_entry_t;
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typedef u_int64_t pdp_entry_t;
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typedef u_int64_t pml4_entry_t;
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#define PML4ESHIFT (3)
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#define PDPESHIFT (3)
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#define PTESHIFT (3)
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#define PDESHIFT (3)
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/*
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* Address of current address space page table maps and directories.
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*/
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#ifdef _KERNEL
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#define addr_PTmap (KVADDR(PML4PML4I, 0, 0, 0))
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#define addr_PDmap (KVADDR(PML4PML4I, PML4PML4I, 0, 0))
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#define addr_PDPmap (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0))
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#define addr_PML4map (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I))
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#define addr_PML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t)))
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#define PTmap ((pt_entry_t *)(addr_PTmap))
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#define PDmap ((pd_entry_t *)(addr_PDmap))
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#define PDPmap ((pd_entry_t *)(addr_PDPmap))
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#define PML4map ((pd_entry_t *)(addr_PML4map))
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#define PML4pml4e ((pd_entry_t *)(addr_PML4pml4e))
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extern u_int64_t KPDPphys; /* physical address of kernel level 3 */
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extern u_int64_t KPML4phys; /* physical address of kernel level 4 */
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/*
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* virtual address to page table entry and
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* to physical address.
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* Note: these work recursively, thus vtopte of a pte will give
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* the corresponding pde that in turn maps it.
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*/
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pt_entry_t *vtopte(vm_offset_t);
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#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
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static __inline pt_entry_t
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pte_load(pt_entry_t *ptep)
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{
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pt_entry_t r;
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r = *ptep;
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return (r);
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}
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static __inline pt_entry_t
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pte_load_store(pt_entry_t *ptep, pt_entry_t pte)
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{
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pt_entry_t r;
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__asm __volatile(
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"xchgq %0,%1"
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: "=m" (*ptep),
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"=r" (r)
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: "1" (pte),
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"m" (*ptep));
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return (r);
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}
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#define pte_load_clear(pte) atomic_readandclear_long(pte)
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static __inline void
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pte_store(pt_entry_t *ptep, pt_entry_t pte)
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{
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*ptep = pte;
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}
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#define pte_clear(ptep) pte_store((ptep), (pt_entry_t)0ULL)
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#define pde_store(pdep, pde) pte_store((pdep), (pde))
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extern pt_entry_t pg_nx;
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#endif /* _KERNEL */
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/*
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* Pmap stuff
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*/
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struct pv_entry;
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struct pv_chunk;
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struct md_page {
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TAILQ_HEAD(,pv_entry) pv_list;
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int pat_mode;
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};
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/*
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* The kernel virtual address (KVA) of the level 4 page table page is always
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* within the direct map (DMAP) region.
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*/
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struct pmap {
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struct mtx pm_mtx;
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pml4_entry_t *pm_pml4; /* KVA of level 4 page table */
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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cpuset_t pm_active; /* active on cpus */
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/* spare u_int here due to padding */
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struct pmap_statistics pm_stats; /* pmap statistics */
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vm_page_t pm_root; /* spare page table pages */
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};
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typedef struct pmap *pmap_t;
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_store;
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#define kernel_pmap (&kernel_pmap_store)
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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#define PMAP_LOCK_ASSERT(pmap, type) \
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mtx_assert(&(pmap)->pm_mtx, (type))
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#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
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#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
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NULL, MTX_DEF | MTX_DUPOK)
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#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
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#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
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#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
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#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
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#endif
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/*
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* For each vm_page_t, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_list.
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*/
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typedef struct pv_entry {
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_list;
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} *pv_entry_t;
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/*
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* pv_entries are allocated in chunks per-process. This avoids the
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* need to track per-pmap assignments.
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*/
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#define _NPCM 3
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#define _NPCPV 168
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struct pv_chunk {
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pmap_t pc_pmap;
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TAILQ_ENTRY(pv_chunk) pc_list;
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uint64_t pc_map[_NPCM]; /* bitmap; 1 = free */
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TAILQ_ENTRY(pv_chunk) pc_lru;
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struct pv_entry pc_pventry[_NPCPV];
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};
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#ifdef _KERNEL
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extern caddr_t CADDR1;
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extern pt_entry_t *CMAP1;
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extern vm_paddr_t phys_avail[];
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extern vm_paddr_t dump_avail[];
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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#define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
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#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
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#define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
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void pmap_bootstrap(vm_paddr_t *);
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int pmap_change_attr(vm_offset_t, vm_size_t, int);
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void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate);
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void pmap_init_pat(void);
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void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
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void *pmap_kenter_temporary(vm_paddr_t pa, int i);
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vm_paddr_t pmap_kextract(vm_offset_t);
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void pmap_kremove(vm_offset_t);
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void *pmap_mapbios(vm_paddr_t, vm_size_t);
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void *pmap_mapdev(vm_paddr_t, vm_size_t);
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void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
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boolean_t pmap_page_is_mapped(vm_page_t m);
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void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
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void pmap_unmapdev(vm_offset_t, vm_size_t);
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void pmap_invalidate_page(pmap_t, vm_offset_t);
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void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
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void pmap_invalidate_all(pmap_t);
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void pmap_invalidate_cache(void);
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void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
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void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
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#endif /* _KERNEL */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PMAP_H_ */
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