26c048c814
supply the addresses for the DPLL register blocks) by hard-coding the addresses in the driver source code. Yes, this is just as bad an idea as it sounds, but we have no choice. In the early days of using fdt data, when we were making up our own data for each board, we defined 4 sets of memory mapped registers in the data. The vendor-supplied data only provides the address of the CCM register block, but not the 3 DPLL blocks. The linux driver has the DPLL physical addresses (which differ by SOC type) hard-coded in the driver, and we have no choice but to do the same thing if we want to run with the vendor- supplied fdt data. So now we use bus_space_map() to make the DPLL blocks accessible, choosing the set of fixed addresses to map based on the soc id. |
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.. | ||
allwinner | ||
altera/socfpga | ||
amlogic/aml8726 | ||
annapurna/alpine | ||
arm | ||
at91 | ||
broadcom/bcm2835 | ||
cavium/cns11xx | ||
cloudabi32 | ||
conf | ||
freescale | ||
include | ||
lpc | ||
mv | ||
nvidia | ||
qemu | ||
rockchip | ||
samsung/exynos | ||
ti | ||
versatile | ||
xilinx | ||
xscale |