e53ea2ab77
- add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor)
53 lines
2.1 KiB
C
53 lines
2.1 KiB
C
/*-
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* Copyright (c) 2009 Alan L. Cox <alc@cs.rice.edu>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_VM_H_
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#define _MACHINE_VM_H_
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#ifdef ARM_NEW_PMAP
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#include <machine/pte-v6.h>
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#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA)
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#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE)
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#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE)
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#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO)
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#define VM_MEMATTR_WT ((vm_memattr_t)PTE2_ATTR_WT)
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#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA
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#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */
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#define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WT /* for DRM */
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#define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */
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#else
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/* Memory attribute configuration. */
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#define VM_MEMATTR_DEFAULT 0
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#define VM_MEMATTR_UNCACHEABLE 1
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#endif
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#endif /* !_MACHINE_VM_H_ */
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