bfc8500c34
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers. Submitted by: jfv@ MFC after: 1 week
571 lines
21 KiB
C
571 lines
21 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_intel_chipinit(device_t dev);
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static int ata_intel_ch_attach(device_t dev);
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static void ata_intel_reset(device_t dev);
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static int ata_intel_old_setmode(device_t dev, int target, int mode);
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static int ata_intel_new_setmode(device_t dev, int target, int mode);
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static int ata_intel_sch_setmode(device_t dev, int target, int mode);
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static int ata_intel_sata_getrev(device_t dev, int target);
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static int ata_intel_31244_ch_attach(device_t dev);
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static int ata_intel_31244_ch_detach(device_t dev);
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static int ata_intel_31244_status(device_t dev);
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static void ata_intel_31244_tf_write(struct ata_request *request);
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static void ata_intel_31244_reset(device_t dev);
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/* misc defines */
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#define INTEL_AHCI 1
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/*
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* Intel chipset support functions
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*/
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static int
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ata_intel_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static struct ata_chip_id ids[] =
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{{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" },
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{ ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" },
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{ ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" },
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{ ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
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{ ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
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{ ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" },
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{ ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" },
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{ ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" },
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{ ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" },
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{ ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" },
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{ ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" },
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{ ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" },
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{ ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" },
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{ ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" },
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{ ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" },
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{ ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" },
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{ ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" },
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{ ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" },
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{ ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" },
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{ ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" },
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{ ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
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{ ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
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{ ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
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{ ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
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{ ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
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{ ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
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{ ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
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{ ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
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{ ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
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{ ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
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{ ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
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{ ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
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{ ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
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{ ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
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{ ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
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{ ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
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{ ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
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{ ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
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{ ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
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{ ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
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{ ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
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{ ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
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{ ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
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{ ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
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{ ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
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{ ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
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{ ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
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{ ATA_5Series_S1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S5, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S6, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_CPT_S1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_S2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_S3, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_CPT_S4, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
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{ ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
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{ ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_INTEL_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_intel_chipinit;
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ata_intel_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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/* good old PIIX needs special treatment (not implemented) */
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if (ctlr->chip->chipid == ATA_I82371FB) {
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ctlr->setmode = ata_intel_old_setmode;
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}
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/* the intel 31244 needs special care if in DPA mode */
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else if (ctlr->chip->chipid == ATA_I31244) {
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if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(0);
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if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2,
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RF_ACTIVE)))
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return ENXIO;
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ctlr->channels = 4;
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ctlr->ch_attach = ata_intel_31244_ch_attach;
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ctlr->ch_detach = ata_intel_31244_ch_detach;
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ctlr->reset = ata_intel_31244_reset;
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}
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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}
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/* SCH */
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else if (ctlr->chip->chipid == ATA_ISCH) {
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ctlr->channels = 1;
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ctlr->ch_attach = ata_intel_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->setmode = ata_intel_sch_setmode;
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}
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/* non SATA intel chips goes here */
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else if (ctlr->chip->max_dma < ATA_SA150) {
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ctlr->channels = ctlr->chip->cfg2;
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ctlr->ch_attach = ata_intel_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->setmode = ata_intel_new_setmode;
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}
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/* SATA parts can be either compat or AHCI */
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else {
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/* force all ports active "the legacy way" */
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pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
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ctlr->ch_attach = ata_intel_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->reset = ata_intel_reset;
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/*
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* if we have AHCI capability and AHCI or RAID mode enabled
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* in BIOS we try for AHCI mode
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*/
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if ((ctlr->chip->cfg1 == INTEL_AHCI) &&
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(pci_read_config(dev, 0x90, 1) & 0xc0) &&
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(ata_ahci_chipinit(dev) != ENXIO))
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return 0;
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/* if BAR(5) is IO it should point to SATA interface registers */
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ctlr->r_type2 = SYS_RES_IOPORT;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE)))
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ctlr->getrev = ata_intel_sata_getrev;
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ctlr->setmode = ata_sata_setmode;
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}
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return 0;
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}
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static int
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ata_intel_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return ENXIO;
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/* if r_res2 is valid it points to SATA interface registers */
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if (ctlr->r_res2) {
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ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
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ch->r_io[ATA_IDX_ADDR].offset = 0x00;
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ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
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ch->r_io[ATA_IDX_DATA].offset = 0x04;
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}
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ch->flags |= ATA_ALWAYS_DMASTAT;
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if (ctlr->chip->max_dma >= ATA_SA150) {
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if (ctlr->chip->cfg1 == 0 &&
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(pci_read_config(device_get_parent(dev), 0x90, 1) & 0x04) == 0)
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_SATA;
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} else if (ctlr->chip->chipid != ATA_ISCH)
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ch->flags |= ATA_CHECKS_CABLE;
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return 0;
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}
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static void
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ata_intel_reset(device_t dev)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int mask, timeout;
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/* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
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if (ctlr->chip->cfg1) {
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mask = (0x0005 << ch->unit);
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}
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else {
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/* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
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if (pci_read_config(parent, 0x90, 1) & 0x04)
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mask = 0x0003;
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else
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mask = (0x0001 << ch->unit);
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}
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pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
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DELAY(10);
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pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
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/* wait up to 1 sec for "connect well" */
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for (timeout = 0; timeout < 100 ; timeout++) {
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if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
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(ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
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break;
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ata_udelay(10000);
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}
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ata_generic_reset(dev);
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}
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static int
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ata_intel_old_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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mode = min(mode, ctlr->chip->max_dma);
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return (mode);
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}
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static int
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ata_intel_new_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int piomode;
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u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
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u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
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u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
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u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
|
|
u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
|
|
u_int32_t mask40 = 0, new40 = 0;
|
|
u_int8_t mask44 = 0, new44 = 0;
|
|
u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
|
|
u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
|
|
|
|
mode = min(mode, ctlr->chip->max_dma);
|
|
if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
|
|
!(reg54 & (0x10 << devno))) {
|
|
ata_print_cable(dev, "controller");
|
|
mode = ATA_UDMA2;
|
|
}
|
|
/* Enable/disable UDMA and set timings. */
|
|
if (mode >= ATA_UDMA0) {
|
|
pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
|
|
pci_write_config(parent, 0x4a,
|
|
(reg4a & ~(0x3 << (devno << 2))) |
|
|
(utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
|
|
piomode = ATA_PIO4;
|
|
} else {
|
|
pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
|
|
pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
|
|
piomode = mode;
|
|
}
|
|
reg54 |= 0x0400;
|
|
/* Set UDMA reference clock (33/66/133MHz). */
|
|
reg54 &= ~(0x1001 << devno);
|
|
if (mode >= ATA_UDMA5)
|
|
reg54 |= (0x1000 << devno);
|
|
else if (mode >= ATA_UDMA3)
|
|
reg54 |= (0x1 << devno);
|
|
pci_write_config(parent, 0x54, reg54, 2);
|
|
/* Allow PIO/WDMA timing controls. */
|
|
reg40 &= ~0x00ff00ff;
|
|
reg40 |= 0x40774077;
|
|
/* Set PIO/WDMA timings. */
|
|
if (target == 0) {
|
|
mask40 = 0x3300;
|
|
new40 = timings[ata_mode2idx(piomode)] << 8;
|
|
} else {
|
|
mask44 = 0x0f;
|
|
new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
|
|
(timings[ata_mode2idx(piomode)] & 0x03);
|
|
}
|
|
if (ch->unit) {
|
|
mask40 <<= 16;
|
|
new40 <<= 16;
|
|
mask44 <<= 4;
|
|
new44 <<= 4;
|
|
}
|
|
pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
|
|
pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
|
|
return (mode);
|
|
}
|
|
|
|
static int
|
|
ata_intel_sch_setmode(device_t dev, int target, int mode)
|
|
{
|
|
device_t parent = device_get_parent(dev);
|
|
struct ata_pci_controller *ctlr = device_get_softc(parent);
|
|
u_int8_t dtim = 0x80 + (target << 2);
|
|
u_int32_t tim = pci_read_config(parent, dtim, 4);
|
|
int piomode;
|
|
|
|
mode = min(mode, ctlr->chip->max_dma);
|
|
if (mode >= ATA_UDMA0) {
|
|
tim |= (0x1 << 31);
|
|
tim &= ~(0x7 << 16);
|
|
tim |= ((mode & ATA_MODE_MASK) << 16);
|
|
piomode = ATA_PIO4;
|
|
} else if (mode >= ATA_WDMA0) {
|
|
tim &= ~(0x1 << 31);
|
|
tim &= ~(0x3 << 8);
|
|
tim |= ((mode & ATA_MODE_MASK) << 8);
|
|
piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
|
|
(mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
|
|
} else
|
|
piomode = mode;
|
|
tim &= ~(0x7);
|
|
tim |= (piomode & 0x7);
|
|
pci_write_config(parent, dtim, tim, 4);
|
|
return (mode);
|
|
}
|
|
|
|
static int
|
|
ata_intel_sata_getrev(device_t dev, int target)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
int devno = (ch->unit << 1) + target;
|
|
|
|
/* set ATA_SSTATUS register offset */
|
|
ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
|
|
/* query SATA STATUS for the speed */
|
|
return ((ATA_IDX_INL(ch, ATA_IDX_DATA) & 0x0f0) >> 4);
|
|
}
|
|
|
|
static int
|
|
ata_intel_31244_ch_attach(device_t dev)
|
|
{
|
|
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
int i;
|
|
int ch_offset;
|
|
|
|
ata_pci_dmainit(dev);
|
|
|
|
ch_offset = 0x200 + ch->unit * 0x200;
|
|
|
|
for (i = ATA_DATA; i < ATA_MAX_RES; i++)
|
|
ch->r_io[i].res = ctlr->r_res2;
|
|
|
|
/* setup ATA registers */
|
|
ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
|
|
ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
|
|
ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
|
|
ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
|
|
ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
|
|
ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
|
|
ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
|
|
ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
|
|
ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
|
|
ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
|
|
ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
|
|
ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
|
|
|
|
/* setup DMA registers */
|
|
ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
|
|
ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
|
|
ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
|
|
|
|
/* setup SATA registers */
|
|
ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
|
|
ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
|
|
ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
|
|
|
|
ch->flags |= ATA_NO_SLAVE;
|
|
ch->flags |= ATA_SATA;
|
|
ata_pci_hw(dev);
|
|
ch->hw.status = ata_intel_31244_status;
|
|
ch->hw.tf_write = ata_intel_31244_tf_write;
|
|
|
|
/* enable PHY state change interrupt */
|
|
ATA_OUTL(ctlr->r_res2, 0x4,
|
|
ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ata_intel_31244_ch_detach(device_t dev)
|
|
{
|
|
|
|
ata_pci_dmafini(dev);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ata_intel_31244_status(device_t dev)
|
|
{
|
|
/* do we have any PHY events ? */
|
|
ata_sata_phy_check_events(dev);
|
|
|
|
/* any drive action to take care of ? */
|
|
return ata_pci_status(dev);
|
|
}
|
|
|
|
static void
|
|
ata_intel_31244_tf_write(struct ata_request *request)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
#ifndef ATA_CAM
|
|
struct ata_device *atadev = device_get_softc(request->dev);
|
|
#endif
|
|
|
|
if (request->flags & ATA_R_48BIT) {
|
|
ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
|
|
ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
|
|
ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
|
|
(request->u.ata.lba & 0x00ff));
|
|
ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
|
|
((request->u.ata.lba >> 8) & 0x00ff));
|
|
ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
|
|
((request->u.ata.lba >> 16) & 0x00ff));
|
|
ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
|
|
}
|
|
else {
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
|
|
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
|
|
#ifndef ATA_CAM
|
|
if (atadev->flags & ATA_D_USE_CHS) {
|
|
int heads, sectors;
|
|
|
|
if (atadev->param.atavalid & ATA_FLAG_54_58) {
|
|
heads = atadev->param.current_heads;
|
|
sectors = atadev->param.current_sectors;
|
|
}
|
|
else {
|
|
heads = atadev->param.heads;
|
|
sectors = atadev->param.sectors;
|
|
}
|
|
ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB,
|
|
(request->u.ata.lba / (sectors * heads)));
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB,
|
|
(request->u.ata.lba / (sectors * heads)) >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
|
|
(((request->u.ata.lba% (sectors * heads)) /
|
|
sectors) & 0xf));
|
|
}
|
|
else {
|
|
#endif
|
|
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE,
|
|
ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
|
|
((request->u.ata.lba >> 24) & 0x0f));
|
|
#ifndef ATA_CAM
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static void
|
|
ata_intel_31244_reset(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
if (ata_sata_phy_reset(dev, -1, 1))
|
|
ata_generic_reset(dev);
|
|
else
|
|
ch->devices = 0;
|
|
}
|
|
|
|
ATA_DECLARE_DRIVER(ata_intel);
|
|
MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);
|