5ee171d264
Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)icu.h 5.6 (Berkeley) 5/9/91
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* $FreeBSD$
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*/
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/*
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* AT/386 Interrupt Control constants
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* W. Jolitz 8/89
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*/
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#ifndef _I386_ISA_ICU_H_
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#define _I386_ISA_ICU_H_
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#ifndef LOCORE
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/*
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#define MP_SAFE
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* Note:
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* Most of the SMP equivilants of the icu macros are coded
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* elsewhere in an MP-safe fashion.
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* In particular note that the 'imen' variable is opaque.
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* DO NOT access imen directly, use INTREN()/INTRDIS().
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*/
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void INTREN __P((u_int));
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void INTRDIS __P((u_int));
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#ifdef APIC_IO
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extern unsigned apic_imen; /* APIC interrupt mask enable */
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#define APIC_IMEN_BITS 32 /* number of bits in apic_imen */
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#else
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extern unsigned imen; /* interrupt mask enable */
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#define IMEN_BITS 16 /* number of bits in imen */
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#endif
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#endif /* LOCORE */
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#ifdef APIC_IO
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/*
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* Note: The APIC uses different values for IRQxxx.
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* Unfortunately many drivers use the 8259 values as indexes
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* into tables, etc. The APIC equivilants are kept as APIC_IRQxxx.
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* The 8259 versions have to be used in SMP for legacy operation
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* of the drivers.
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*/
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#endif /* APIC_IO */
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/*
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* Interrupt enable bits - in normal order of priority (which we change)
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*/
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#define IRQ0 0x0001 /* highest priority - timer */
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#define IRQ1 0x0002
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#define IRQ_SLAVE 0x0004
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#define IRQ8 0x0100
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#define IRQ9 0x0200
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#define IRQ2 IRQ9
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#define IRQ10 0x0400
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#define IRQ11 0x0800
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#define IRQ12 0x1000
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#define IRQ13 0x2000
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#define IRQ14 0x4000
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#define IRQ15 0x8000
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#define IRQ3 0x0008 /* this is highest after rotation */
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#define IRQ4 0x0010
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#define IRQ5 0x0020
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#define IRQ6 0x0040
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#define IRQ7 0x0080 /* lowest - parallel printer */
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#ifdef PC98
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#undef IRQ2
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#define IRQ2 0x0004
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#undef IRQ_SLAVE
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#define IRQ_SLAVE 0x0080
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#endif
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/*
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* Interrupt Control offset into Interrupt descriptor table (IDT)
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*/
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#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
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#ifdef APIC_IO
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/* 32-47: ISA IRQ0-IRQ15, 48-55: IO APIC IRQ16-IRQ23 */
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#define ICU_LEN 24
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#else
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#define ICU_LEN 16 /* 32-47 are ISA interrupts */
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#endif /* APIC_IO */
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#endif /* !_I386_ISA_ICU_H_ */
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