697 lines
18 KiB
C
697 lines
18 KiB
C
/*-
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* Copyright (c) 2008 Marcel Moolenaar
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* Copyright (c) 2001 Benno Rice
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* Copyright (c) 2001 David E. O'Brien
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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/*
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* The __ATOMIC_REL/ACQ() macros provide memory barriers only in conjunction
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* with the atomic lXarx/stXcx. sequences below. They are not exposed outside
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* of this file. See also Appendix B.2 of Book II of the architecture manual.
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*
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* Note that not all Book-E processors accept the light-weight sync variant.
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* In particular, early models of E500 cores are known to wedge. Bank on all
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* 64-bit capable CPUs to accept lwsync properly and pressimize 32-bit CPUs
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* to use the heavier-weight sync.
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*/
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#ifdef __powerpc64__
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#define mb() __asm __volatile("lwsync" : : : "memory")
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#define rmb() __asm __volatile("lwsync" : : : "memory")
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#define wmb() __asm __volatile("lwsync" : : : "memory")
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#define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory")
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#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory")
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#else
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#define mb() __asm __volatile("sync" : : : "memory")
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#define rmb() __asm __volatile("sync" : : : "memory")
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#define wmb() __asm __volatile("sync" : : : "memory")
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#define __ATOMIC_REL() __asm __volatile("sync" : : : "memory")
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#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory")
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#endif
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/*
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* atomic_add(p, v)
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* { *p += v; }
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*/
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#define __atomic_add_int(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" add %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_add_int */
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#ifdef __powerpc64__
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#define __atomic_add_long(p, v, t) \
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__asm __volatile( \
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"1: ldarx %0, 0, %2\n" \
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" add %0, %3, %0\n" \
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" stdcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_add_long */
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#else
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#define __atomic_add_long(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" add %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_add_long */
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#endif
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#define _ATOMIC_ADD(type) \
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static __inline void \
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atomic_add_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_add_##type(p, v, t); \
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} \
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\
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static __inline void \
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atomic_add_acq_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_add_##type(p, v, t); \
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__ATOMIC_ACQ(); \
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} \
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\
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static __inline void \
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atomic_add_rel_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__ATOMIC_REL(); \
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__atomic_add_##type(p, v, t); \
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} \
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/* _ATOMIC_ADD */
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_ATOMIC_ADD(int)
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_ATOMIC_ADD(long)
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#define atomic_add_32 atomic_add_int
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#define atomic_add_acq_32 atomic_add_acq_int
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#define atomic_add_rel_32 atomic_add_rel_int
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#ifdef __powerpc64__
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#define atomic_add_64 atomic_add_long
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#define atomic_add_acq_64 atomic_add_acq_long
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#define atomic_add_rel_64 atomic_add_rel_long
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#define atomic_add_ptr atomic_add_long
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#define atomic_add_acq_ptr atomic_add_acq_long
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#define atomic_add_rel_ptr atomic_add_rel_long
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#else
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#define atomic_add_ptr atomic_add_int
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#define atomic_add_acq_ptr atomic_add_acq_int
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#define atomic_add_rel_ptr atomic_add_rel_int
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#endif
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#undef _ATOMIC_ADD
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#undef __atomic_add_long
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#undef __atomic_add_int
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/*
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* atomic_clear(p, v)
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* { *p &= ~v; }
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*/
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#define __atomic_clear_int(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" andc %0, %0, %3\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_clear_int */
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#ifdef __powerpc64__
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#define __atomic_clear_long(p, v, t) \
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__asm __volatile( \
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"1: ldarx %0, 0, %2\n" \
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" andc %0, %0, %3\n" \
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" stdcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_clear_long */
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#else
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#define __atomic_clear_long(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" andc %0, %0, %3\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_clear_long */
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#endif
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#define _ATOMIC_CLEAR(type) \
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static __inline void \
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atomic_clear_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_clear_##type(p, v, t); \
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} \
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\
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static __inline void \
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atomic_clear_acq_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_clear_##type(p, v, t); \
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__ATOMIC_ACQ(); \
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} \
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\
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static __inline void \
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atomic_clear_rel_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__ATOMIC_REL(); \
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__atomic_clear_##type(p, v, t); \
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} \
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/* _ATOMIC_CLEAR */
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_ATOMIC_CLEAR(int)
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_ATOMIC_CLEAR(long)
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#define atomic_clear_32 atomic_clear_int
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#define atomic_clear_acq_32 atomic_clear_acq_int
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#define atomic_clear_rel_32 atomic_clear_rel_int
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#ifdef __powerpc64__
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#define atomic_clear_64 atomic_clear_long
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#define atomic_clear_acq_64 atomic_clear_acq_long
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#define atomic_clear_rel_64 atomic_clear_rel_long
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#define atomic_clear_ptr atomic_clear_long
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#define atomic_clear_acq_ptr atomic_clear_acq_long
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#define atomic_clear_rel_ptr atomic_clear_rel_long
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#else
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#define atomic_clear_ptr atomic_clear_int
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#define atomic_clear_acq_ptr atomic_clear_acq_int
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#define atomic_clear_rel_ptr atomic_clear_rel_int
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#endif
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#undef _ATOMIC_CLEAR
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#undef __atomic_clear_long
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#undef __atomic_clear_int
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/*
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* atomic_cmpset(p, o, n)
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*/
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/* TODO -- see below */
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/*
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* atomic_load_acq(p)
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*/
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/* TODO -- see below */
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/*
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* atomic_readandclear(p)
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*/
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/* TODO -- see below */
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/*
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* atomic_set(p, v)
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* { *p |= v; }
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*/
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#define __atomic_set_int(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" or %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_set_int */
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#ifdef __powerpc64__
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#define __atomic_set_long(p, v, t) \
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__asm __volatile( \
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"1: ldarx %0, 0, %2\n" \
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" or %0, %3, %0\n" \
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" stdcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_set_long */
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#else
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#define __atomic_set_long(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" or %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_set_long */
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#endif
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#define _ATOMIC_SET(type) \
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static __inline void \
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atomic_set_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_set_##type(p, v, t); \
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} \
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\
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static __inline void \
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atomic_set_acq_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_set_##type(p, v, t); \
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__ATOMIC_ACQ(); \
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} \
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\
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static __inline void \
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atomic_set_rel_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__ATOMIC_REL(); \
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__atomic_set_##type(p, v, t); \
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} \
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/* _ATOMIC_SET */
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_ATOMIC_SET(int)
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_ATOMIC_SET(long)
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#define atomic_set_32 atomic_set_int
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#define atomic_set_acq_32 atomic_set_acq_int
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#define atomic_set_rel_32 atomic_set_rel_int
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#ifdef __powerpc64__
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#define atomic_set_64 atomic_set_long
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#define atomic_set_acq_64 atomic_set_acq_long
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#define atomic_set_rel_64 atomic_set_rel_long
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#define atomic_set_ptr atomic_set_long
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#define atomic_set_acq_ptr atomic_set_acq_long
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#define atomic_set_rel_ptr atomic_set_rel_long
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#else
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#define atomic_set_ptr atomic_set_int
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#define atomic_set_acq_ptr atomic_set_acq_int
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#define atomic_set_rel_ptr atomic_set_rel_int
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#endif
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#undef _ATOMIC_SET
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#undef __atomic_set_long
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#undef __atomic_set_int
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/*
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* atomic_subtract(p, v)
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* { *p -= v; }
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*/
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#define __atomic_subtract_int(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" subf %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_subtract_int */
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#ifdef __powerpc64__
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#define __atomic_subtract_long(p, v, t) \
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__asm __volatile( \
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"1: ldarx %0, 0, %2\n" \
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" subf %0, %3, %0\n" \
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" stdcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_subtract_long */
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#else
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#define __atomic_subtract_long(p, v, t) \
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__asm __volatile( \
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"1: lwarx %0, 0, %2\n" \
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" subf %0, %3, %0\n" \
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" stwcx. %0, 0, %2\n" \
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" bne- 1b\n" \
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: "=&r" (t), "=m" (*p) \
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: "r" (p), "r" (v), "m" (*p) \
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: "cc", "memory") \
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/* __atomic_subtract_long */
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#endif
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#define _ATOMIC_SUBTRACT(type) \
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static __inline void \
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atomic_subtract_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_subtract_##type(p, v, t); \
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} \
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\
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static __inline void \
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atomic_subtract_acq_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__atomic_subtract_##type(p, v, t); \
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__ATOMIC_ACQ(); \
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} \
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\
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static __inline void \
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atomic_subtract_rel_##type(volatile u_##type *p, u_##type v) { \
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u_##type t; \
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__ATOMIC_REL(); \
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__atomic_subtract_##type(p, v, t); \
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} \
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/* _ATOMIC_SUBTRACT */
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_ATOMIC_SUBTRACT(int)
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_ATOMIC_SUBTRACT(long)
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#define atomic_subtract_32 atomic_subtract_int
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#define atomic_subtract_acq_32 atomic_subtract_acq_int
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#define atomic_subtract_rel_32 atomic_subtract_rel_int
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#ifdef __powerpc64__
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#define atomic_subtract_64 atomic_subtract_long
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#define atomic_subtract_acq_64 atomic_subract_acq_long
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#define atomic_subtract_rel_64 atomic_subtract_rel_long
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#define atomic_subtract_ptr atomic_subtract_long
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#define atomic_subtract_acq_ptr atomic_subtract_acq_long
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#define atomic_subtract_rel_ptr atomic_subtract_rel_long
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#else
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#define atomic_subtract_ptr atomic_subtract_int
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#define atomic_subtract_acq_ptr atomic_subtract_acq_int
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#define atomic_subtract_rel_ptr atomic_subtract_rel_int
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#endif
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#undef _ATOMIC_SUBTRACT
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#undef __atomic_subtract_long
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#undef __atomic_subtract_int
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/*
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* atomic_store_rel(p, v)
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*/
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/* TODO -- see below */
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/*
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* Old/original implementations that still need revisiting.
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*/
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static __inline u_int
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atomic_readandclear_int(volatile u_int *addr)
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{
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u_int result,temp;
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#ifdef __GNUCLIKE_ASM
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__asm __volatile (
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"\tsync\n" /* drain writes */
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"1:\tlwarx %0, 0, %3\n\t" /* load old value */
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"li %1, 0\n\t" /* load new value */
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"stwcx. %1, 0, %3\n\t" /* attempt to store */
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"bne- 1b\n\t" /* spin if failed */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "r" (addr), "m" (*addr)
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: "cc", "memory");
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#endif
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return (result);
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}
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#ifdef __powerpc64__
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static __inline u_long
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atomic_readandclear_long(volatile u_long *addr)
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{
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u_long result,temp;
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#ifdef __GNUCLIKE_ASM
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__asm __volatile (
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"\tsync\n" /* drain writes */
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"1:\tldarx %0, 0, %3\n\t" /* load old value */
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"li %1, 0\n\t" /* load new value */
|
|
"stdcx. %1, 0, %3\n\t" /* attempt to store */
|
|
"bne- 1b\n\t" /* spin if failed */
|
|
: "=&r"(result), "=&r"(temp), "=m" (*addr)
|
|
: "r" (addr), "m" (*addr)
|
|
: "cc", "memory");
|
|
#endif
|
|
|
|
return (result);
|
|
}
|
|
#endif
|
|
|
|
#define atomic_readandclear_32 atomic_readandclear_int
|
|
|
|
#ifdef __powerpc64__
|
|
#define atomic_readandclear_64 atomic_readandclear_long
|
|
|
|
#define atomic_readandclear_ptr atomic_readandclear_long
|
|
#else
|
|
static __inline u_long
|
|
atomic_readandclear_long(volatile u_long *addr)
|
|
{
|
|
|
|
return ((u_long)atomic_readandclear_int((volatile u_int *)addr));
|
|
}
|
|
|
|
#define atomic_readandclear_ptr atomic_readandclear_int
|
|
#endif
|
|
|
|
/*
|
|
* We assume that a = b will do atomic loads and stores.
|
|
*/
|
|
#define ATOMIC_STORE_LOAD(TYPE) \
|
|
static __inline u_##TYPE \
|
|
atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
|
|
{ \
|
|
u_##TYPE v; \
|
|
\
|
|
v = *p; \
|
|
mb(); \
|
|
return (v); \
|
|
} \
|
|
\
|
|
static __inline void \
|
|
atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \
|
|
{ \
|
|
mb(); \
|
|
*p = v; \
|
|
}
|
|
|
|
ATOMIC_STORE_LOAD(int)
|
|
|
|
#define atomic_load_acq_32 atomic_load_acq_int
|
|
#define atomic_store_rel_32 atomic_store_rel_int
|
|
|
|
#ifdef __powerpc64__
|
|
ATOMIC_STORE_LOAD(long)
|
|
|
|
#define atomic_load_acq_64 atomic_load_acq_long
|
|
#define atomic_store_rel_64 atomic_store_rel_long
|
|
|
|
#define atomic_load_acq_ptr atomic_load_acq_long
|
|
#define atomic_store_rel_ptr atomic_store_rel_long
|
|
#else
|
|
static __inline u_long
|
|
atomic_load_acq_long(volatile u_long *addr)
|
|
{
|
|
|
|
return ((u_long)atomic_load_acq_int((volatile u_int *)addr));
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_rel_long(volatile u_long *addr, u_long val)
|
|
{
|
|
|
|
atomic_store_rel_int((volatile u_int *)addr, (u_int)val);
|
|
}
|
|
|
|
#define atomic_load_acq_ptr atomic_load_acq_int
|
|
#define atomic_store_rel_ptr atomic_store_rel_int
|
|
#endif
|
|
#undef ATOMIC_STORE_LOAD
|
|
|
|
/*
|
|
* Atomically compare the value stored at *p with cmpval and if the
|
|
* two values are equal, update the value of *p with newval. Returns
|
|
* zero if the compare failed, nonzero otherwise.
|
|
*/
|
|
static __inline int
|
|
atomic_cmpset_int(volatile u_int* p, u_int cmpval, u_int newval)
|
|
{
|
|
int ret;
|
|
|
|
#ifdef __GNUCLIKE_ASM
|
|
__asm __volatile (
|
|
"1:\tlwarx %0, 0, %2\n\t" /* load old value */
|
|
"cmplw %3, %0\n\t" /* compare */
|
|
"bne 2f\n\t" /* exit if not equal */
|
|
"stwcx. %4, 0, %2\n\t" /* attempt to store */
|
|
"bne- 1b\n\t" /* spin if failed */
|
|
"li %0, 1\n\t" /* success - retval = 1 */
|
|
"b 3f\n\t" /* we've succeeded */
|
|
"2:\n\t"
|
|
"stwcx. %0, 0, %2\n\t" /* clear reservation (74xx) */
|
|
"li %0, 0\n\t" /* failure - retval = 0 */
|
|
"3:\n\t"
|
|
: "=&r" (ret), "=m" (*p)
|
|
: "r" (p), "r" (cmpval), "r" (newval), "m" (*p)
|
|
: "cc", "memory");
|
|
#endif
|
|
|
|
return (ret);
|
|
}
|
|
static __inline int
|
|
atomic_cmpset_long(volatile u_long* p, u_long cmpval, u_long newval)
|
|
{
|
|
int ret;
|
|
|
|
#ifdef __GNUCLIKE_ASM
|
|
__asm __volatile (
|
|
#ifdef __powerpc64__
|
|
"1:\tldarx %0, 0, %2\n\t" /* load old value */
|
|
"cmpld %3, %0\n\t" /* compare */
|
|
"bne 2f\n\t" /* exit if not equal */
|
|
"stdcx. %4, 0, %2\n\t" /* attempt to store */
|
|
#else
|
|
"1:\tlwarx %0, 0, %2\n\t" /* load old value */
|
|
"cmplw %3, %0\n\t" /* compare */
|
|
"bne 2f\n\t" /* exit if not equal */
|
|
"stwcx. %4, 0, %2\n\t" /* attempt to store */
|
|
#endif
|
|
"bne- 1b\n\t" /* spin if failed */
|
|
"li %0, 1\n\t" /* success - retval = 1 */
|
|
"b 3f\n\t" /* we've succeeded */
|
|
"2:\n\t"
|
|
#ifdef __powerpc64__
|
|
"stdcx. %0, 0, %2\n\t" /* clear reservation (74xx) */
|
|
#else
|
|
"stwcx. %0, 0, %2\n\t" /* clear reservation (74xx) */
|
|
#endif
|
|
"li %0, 0\n\t" /* failure - retval = 0 */
|
|
"3:\n\t"
|
|
: "=&r" (ret), "=m" (*p)
|
|
: "r" (p), "r" (cmpval), "r" (newval), "m" (*p)
|
|
: "cc", "memory");
|
|
#endif
|
|
|
|
return (ret);
|
|
}
|
|
|
|
static __inline int
|
|
atomic_cmpset_acq_int(volatile u_int *p, u_int cmpval, u_int newval)
|
|
{
|
|
int retval;
|
|
|
|
retval = atomic_cmpset_int(p, cmpval, newval);
|
|
__ATOMIC_ACQ();
|
|
return (retval);
|
|
}
|
|
|
|
static __inline int
|
|
atomic_cmpset_rel_int(volatile u_int *p, u_int cmpval, u_int newval)
|
|
{
|
|
__ATOMIC_REL();
|
|
return (atomic_cmpset_int(p, cmpval, newval));
|
|
}
|
|
|
|
static __inline int
|
|
atomic_cmpset_acq_long(volatile u_long *p, u_long cmpval, u_long newval)
|
|
{
|
|
u_long retval;
|
|
|
|
retval = atomic_cmpset_long(p, cmpval, newval);
|
|
__ATOMIC_ACQ();
|
|
return (retval);
|
|
}
|
|
|
|
static __inline int
|
|
atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval)
|
|
{
|
|
__ATOMIC_REL();
|
|
return (atomic_cmpset_long(p, cmpval, newval));
|
|
}
|
|
|
|
#define atomic_cmpset_32 atomic_cmpset_int
|
|
#define atomic_cmpset_acq_32 atomic_cmpset_acq_int
|
|
#define atomic_cmpset_rel_32 atomic_cmpset_rel_int
|
|
|
|
#ifdef __powerpc64__
|
|
#define atomic_cmpset_64 atomic_cmpset_long
|
|
#define atomic_cmpset_acq_64 atomic_cmpset_acq_long
|
|
#define atomic_cmpset_rel_64 atomic_cmpset_rel_long
|
|
|
|
#define atomic_cmpset_ptr atomic_cmpset_long
|
|
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_long
|
|
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_long
|
|
#else
|
|
#define atomic_cmpset_ptr atomic_cmpset_int
|
|
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_int
|
|
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_int
|
|
#endif
|
|
|
|
static __inline u_int
|
|
atomic_fetchadd_int(volatile u_int *p, u_int v)
|
|
{
|
|
u_int value;
|
|
|
|
do {
|
|
value = *p;
|
|
} while (!atomic_cmpset_int(p, value, value + v));
|
|
return (value);
|
|
}
|
|
|
|
static __inline u_long
|
|
atomic_fetchadd_long(volatile u_long *p, u_long v)
|
|
{
|
|
u_long value;
|
|
|
|
do {
|
|
value = *p;
|
|
} while (!atomic_cmpset_long(p, value, value + v));
|
|
return (value);
|
|
}
|
|
|
|
#define atomic_fetchadd_32 atomic_fetchadd_int
|
|
|
|
#ifdef __powerpc64__
|
|
#define atomic_fetchadd_64 atomic_fetchadd_long
|
|
#endif
|
|
|
|
#undef __ATOMIC_REL
|
|
#undef __ATOMIC_ACQ
|
|
|
|
#endif /* ! _MACHINE_ATOMIC_H_ */
|