3c3e9d336d
o add HAL_CAP_BSSIDMATCH to identify parts that have the support for disabling bssid match o honor capability for set/get rx filter o use HAL_CAP_BSSIDMATCH in driver to decide whether to use the bssid match disable or fall back to promisc mode Reviewed by: rpaulo Approved by: re (rwatson)
805 lines
25 KiB
C
805 lines
25 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_INTERAL_H_
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#define _ATH_AH_INTERAL_H_
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/*
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* Atheros Device Hardware Access Layer (HAL).
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*
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* Internal definitions.
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*/
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#define AH_NULL 0
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#define AH_MIN(a,b) ((a)<(b)?(a):(b))
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#define AH_MAX(a,b) ((a)>(b)?(a):(b))
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#include <net80211/_ieee80211.h>
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#ifndef NBBY
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#define NBBY 8 /* number of bits/byte */
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#endif
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#ifndef roundup
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#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
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#endif
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#ifndef howmany
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#define howmany(x, y) (((x)+((y)-1))/(y))
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#endif
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#ifndef offsetof
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#define offsetof(type, field) ((size_t)(&((type *)0)->field))
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#endif
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typedef struct {
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uint16_t start; /* first register */
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uint16_t end; /* ending register or zero */
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} HAL_REGRANGE;
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typedef struct {
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uint32_t addr; /* regiser address/offset */
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uint32_t value; /* value to write */
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} HAL_REGWRITE;
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/*
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* Transmit power scale factor.
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*
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* NB: This is not public because we want to discourage the use of
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* scaling; folks should use the tx power limit interface.
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*/
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typedef enum {
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HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
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HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
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HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
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HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
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HAL_TP_SCALE_MIN = 4, /* min, but still on */
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} HAL_TP_SCALE;
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typedef enum {
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HAL_CAP_RADAR = 0, /* Radar capability */
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HAL_CAP_AR = 1, /* AR capability */
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} HAL_PHYDIAG_CAPS;
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/*
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* Each chip or class of chips registers to offer support.
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*/
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struct ath_hal_chip {
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const char *name;
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const char *(*probe)(uint16_t vendorid, uint16_t devid);
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struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
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HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error);
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};
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#ifndef AH_CHIP
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#define AH_CHIP(_name, _probe, _attach) \
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static struct ath_hal_chip _name##_chip = { \
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.name = #_name, \
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.probe = _probe, \
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.attach = _attach \
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}; \
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OS_DATA_SET(ah_chips, _name##_chip)
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#endif
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/*
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* Each RF backend registers to offer support; this is mostly
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* used by multi-chip 5212 solutions. Single-chip solutions
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* have a fixed idea about which RF to use.
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*/
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struct ath_hal_rf {
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const char *name;
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HAL_BOOL (*probe)(struct ath_hal *ah);
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HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
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};
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#ifndef AH_RF
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#define AH_RF(_name, _probe, _attach) \
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static struct ath_hal_rf _name##_rf = { \
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.name = __STRING(_name), \
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.probe = _probe, \
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.attach = _attach \
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}; \
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OS_DATA_SET(ah_rfs, _name##_rf)
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#endif
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struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
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/*
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* Maximum number of internal channels. Entries are per unique
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* frequency so this might be need to be increased to handle all
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* usage cases; typically no more than 32 are really needed but
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* dynamically allocating the data structures is a bit painful
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* right now.
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*/
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#ifndef AH_MAXCHAN
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#define AH_MAXCHAN 96
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#endif
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/*
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* Internal per-channel state. These are found
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* using ic_devdata in the ieee80211_channel.
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*/
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typedef struct {
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uint16_t channel; /* h/w frequency, NB: may be mapped */
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uint8_t privFlags;
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#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
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#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
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#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
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uint8_t calValid; /* bitmask of cal types */
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int8_t iCoff;
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int8_t qCoff;
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int16_t rawNoiseFloor;
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int16_t noiseFloorAdjust;
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uint16_t mainSpur; /* cached spur value for this channel */
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} HAL_CHANNEL_INTERNAL;
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/* channel requires noise floor check */
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#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
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/* all full-width channels */
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#define IEEE80211_CHAN_ALLFULL \
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(IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
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#define IEEE80211_CHAN_ALLTURBOFULL \
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(IEEE80211_CHAN_ALLTURBO - \
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(IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
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typedef struct {
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uint32_t halChanSpreadSupport : 1,
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halSleepAfterBeaconBroken : 1,
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halCompressSupport : 1,
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halBurstSupport : 1,
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halFastFramesSupport : 1,
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halChapTuningSupport : 1,
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halTurboGSupport : 1,
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halTurboPrimeSupport : 1,
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halMicAesCcmSupport : 1,
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halMicCkipSupport : 1,
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halMicTkipSupport : 1,
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halTkipMicTxRxKeySupport : 1,
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halCipherAesCcmSupport : 1,
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halCipherCkipSupport : 1,
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halCipherTkipSupport : 1,
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halPSPollBroken : 1,
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halVEOLSupport : 1,
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halBssIdMaskSupport : 1,
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halMcastKeySrchSupport : 1,
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halTsfAddSupport : 1,
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halChanHalfRate : 1,
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halChanQuarterRate : 1,
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halHTSupport : 1,
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halRfSilentSupport : 1,
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halHwPhyCounterSupport : 1,
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halWowSupport : 1,
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halWowMatchPatternExact : 1,
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halAutoSleepSupport : 1,
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halFastCCSupport : 1,
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halBtCoexSupport : 1;
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uint32_t halRxStbcSupport : 1,
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halTxStbcSupport : 1,
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halGTTSupport : 1,
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halCSTSupport : 1,
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halRifsRxSupport : 1,
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halRifsTxSupport : 1,
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halExtChanDfsSupport : 1,
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halForcePpmSupport : 1,
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halEnhancedPmSupport : 1,
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halMbssidAggrSupport : 1,
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halBssidMatchSupport : 1;
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uint32_t halWirelessModes;
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uint16_t halTotalQueues;
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uint16_t halKeyCacheSize;
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uint16_t halLow5GhzChan, halHigh5GhzChan;
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uint16_t halLow2GhzChan, halHigh2GhzChan;
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int halTstampPrecision;
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int halRtsAggrLimit;
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uint8_t halTxChainMask;
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uint8_t halRxChainMask;
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uint8_t halNumGpioPins;
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uint8_t halNumAntCfg2GHz;
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uint8_t halNumAntCfg5GHz;
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uint32_t halIntrMask;
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} HAL_CAPABILITIES;
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struct regDomain;
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/*
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* The ``private area'' follows immediately after the ``public area''
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* in the data structure returned by ath_hal_attach. Private data are
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* used by device-independent code such as the regulatory domain support.
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* In general, code within the HAL should never depend on data in the
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* public area. Instead any public data needed internally should be
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* shadowed here.
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*
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* When declaring a device-specific ath_hal data structure this structure
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* is assumed to at the front; e.g.
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*
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* struct ath_hal_5212 {
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* struct ath_hal_private ah_priv;
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* ...
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* };
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*
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* It might be better to manage the method pointers in this structure
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* using an indirect pointer to a read-only data structure but this would
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* disallow class-style method overriding.
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*/
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struct ath_hal_private {
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struct ath_hal h; /* public area */
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/* NB: all methods go first to simplify initialization */
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HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
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uint16_t channelFlags,
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uint16_t *lowChannel, uint16_t *highChannel);
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u_int (*ah_getWirelessModes)(struct ath_hal*);
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HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
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uint16_t *data);
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HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
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uint16_t data);
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HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
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struct ieee80211_channel *);
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int16_t (*ah_getNfAdjust)(struct ath_hal *,
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const HAL_CHANNEL_INTERNAL*);
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void (*ah_getNoiseFloor)(struct ath_hal *,
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int16_t nfarray[]);
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void *ah_eeprom; /* opaque EEPROM state */
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uint16_t ah_eeversion; /* EEPROM version */
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void (*ah_eepromDetach)(struct ath_hal *);
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HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
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HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
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uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
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HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
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const void *args, uint32_t argsize,
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void **result, uint32_t *resultsize);
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/*
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* Device revision information.
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*/
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uint16_t ah_devid; /* PCI device ID */
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uint16_t ah_subvendorid; /* PCI subvendor ID */
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uint32_t ah_macVersion; /* MAC version id */
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uint16_t ah_macRev; /* MAC revision */
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uint16_t ah_phyRev; /* PHY revision */
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uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
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uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
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uint8_t ah_ispcie; /* PCIE, special treatment */
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HAL_OPMODE ah_opmode; /* operating mode from reset */
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const struct ieee80211_channel *ah_curchan;/* operating channel */
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HAL_CAPABILITIES ah_caps; /* device capabilities */
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uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
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int16_t ah_powerLimit; /* tx power cap */
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uint16_t ah_maxPowerLevel; /* calculated max tx power */
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u_int ah_tpScale; /* tx power scale factor */
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uint32_t ah_11nCompat; /* 11n compat controls */
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/*
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* State for regulatory domain handling.
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*/
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HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
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HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
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u_int ah_nchan; /* valid items in ah_channels */
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const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
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const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
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uint8_t ah_coverageClass; /* coverage class */
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/*
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* RF Silent handling; setup according to the EEPROM.
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*/
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uint16_t ah_rfsilent; /* GPIO pin + polarity */
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HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
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/*
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* Diagnostic support for discriminating HIUERR reports.
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*/
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uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
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int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
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};
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#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
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#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
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AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
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#define ath_hal_getWirelessModes(_ah) \
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AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
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#define ath_hal_eepromRead(_ah, _off, _data) \
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AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
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#define ath_hal_eepromWrite(_ah, _off, _data) \
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AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
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#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
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(_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
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#define ath_hal_gpioCfgInput(_ah, _gpio) \
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(_ah)->ah_gpioCfgInput(_ah, _gpio)
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#define ath_hal_gpioGet(_ah, _gpio) \
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(_ah)->ah_gpioGet(_ah, _gpio)
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#define ath_hal_gpioSet(_ah, _gpio, _val) \
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(_ah)->ah_gpioSet(_ah, _gpio, _val)
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#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
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(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
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#define ath_hal_getpowerlimits(_ah, _chan) \
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AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
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#define ath_hal_getNfAdjust(_ah, _c) \
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AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
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#define ath_hal_getNoiseFloor(_ah, _nfArray) \
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AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
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#define ath_hal_configPCIE(_ah, _reset) \
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(_ah)->ah_configPCIE(_ah, _reset)
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#define ath_hal_disablePCIE(_ah) \
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(_ah)->ah_disablePCIE(_ah)
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#define ath_hal_eepromDetach(_ah) do { \
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if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
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AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
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} while (0)
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#define ath_hal_eepromGet(_ah, _param, _val) \
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AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
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#define ath_hal_eepromSet(_ah, _param, _val) \
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AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
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#define ath_hal_eepromGetFlag(_ah, _param) \
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(AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
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#define ath_hal_getSpurChan(_ah, _ix, _is2G) \
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AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
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#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
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AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
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#ifndef _NET_IF_IEEE80211_H_
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/*
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* Stuff that would naturally come from _ieee80211.h
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*/
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#define IEEE80211_ADDR_LEN 6
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#define IEEE80211_WEP_IVLEN 3 /* 24bit */
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#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
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#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
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#define IEEE80211_CRC_LEN 4
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#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
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(IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
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#endif /* _NET_IF_IEEE80211_H_ */
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#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
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#define INIT_AIFS 2
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#define INIT_CWMIN 15
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#define INIT_CWMIN_11B 31
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#define INIT_CWMAX 1023
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#define INIT_SH_RETRY 10
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#define INIT_LG_RETRY 10
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#define INIT_SSH_RETRY 32
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#define INIT_SLG_RETRY 32
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typedef struct {
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uint32_t tqi_ver; /* HAL TXQ verson */
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HAL_TX_QUEUE tqi_type; /* hw queue type*/
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HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
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HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
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uint32_t tqi_priority;
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uint32_t tqi_aifs; /* aifs */
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uint32_t tqi_cwmin; /* cwMin */
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uint32_t tqi_cwmax; /* cwMax */
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uint16_t tqi_shretry; /* frame short retry limit */
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uint16_t tqi_lgretry; /* frame long retry limit */
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uint32_t tqi_cbrPeriod;
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uint32_t tqi_cbrOverflowLimit;
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uint32_t tqi_burstTime;
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uint32_t tqi_readyTime;
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uint32_t tqi_physCompBuf;
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uint32_t tqi_intFlags; /* flags for internal use */
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} HAL_TX_QUEUE_INFO;
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extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
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HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
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extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
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HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
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typedef enum {
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HAL_ANI_PRESENT, /* is ANI support present */
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HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */
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HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */
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HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */
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HAL_ANI_FIRSTEP_LEVEL, /* set level */
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HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */
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HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
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HAL_ANI_PHYERR_RESET, /* reset phy error stats */
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} HAL_ANI_CMD;
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#define HAL_SPUR_VAL_MASK 0x3FFF
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#define HAL_SPUR_CHAN_WIDTH 87
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#define HAL_BIN_WIDTH_BASE_100HZ 3125
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#define HAL_BIN_WIDTH_TURBO_100HZ 6250
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#define HAL_MAX_BINS_ALLOWED 28
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#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
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#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
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#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
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/*
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* Deduce if the host cpu has big- or litt-endian byte order.
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*/
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static __inline__ int
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isBigEndian(void)
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{
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union {
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int32_t i;
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char c[4];
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} u;
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u.i = 1;
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return (u.c[0] == 0);
|
|
}
|
|
|
|
/* unalligned little endian access */
|
|
#define LE_READ_2(p) \
|
|
((uint16_t) \
|
|
((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
|
|
#define LE_READ_4(p) \
|
|
((uint32_t) \
|
|
((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
|
|
(((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
|
|
|
|
/*
|
|
* Register manipulation macros that expect bit field defines
|
|
* to follow the convention that an _S suffix is appended for
|
|
* a shift count, while the field mask has no suffix.
|
|
*/
|
|
#define SM(_v, _f) (((_v) << _f##_S) & (_f))
|
|
#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
|
|
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
|
|
OS_REG_WRITE(_a, _r, \
|
|
(OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
|
|
#define OS_REG_SET_BIT(_a, _r, _f) \
|
|
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
|
|
#define OS_REG_CLR_BIT(_a, _r, _f) \
|
|
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
|
|
|
|
/* system-configurable parameters */
|
|
extern int ath_hal_dma_beacon_response_time; /* in TU's */
|
|
extern int ath_hal_sw_beacon_response_time; /* in TU's */
|
|
extern int ath_hal_additional_swba_backoff; /* in TU's */
|
|
|
|
/* wait for the register contents to have the specified value */
|
|
extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
|
|
uint32_t mask, uint32_t val);
|
|
|
|
/* return the first n bits in val reversed */
|
|
extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
|
|
|
|
/* printf interfaces */
|
|
extern void ath_hal_printf(struct ath_hal *, const char*, ...)
|
|
__printflike(2,3);
|
|
extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
|
|
__printflike(2, 0);
|
|
extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
|
|
|
|
/* allocate and free memory */
|
|
extern void *ath_hal_malloc(size_t);
|
|
extern void ath_hal_free(void *);
|
|
|
|
/* common debugging interfaces */
|
|
#ifdef AH_DEBUG
|
|
#include "ah_debug.h"
|
|
extern int ath_hal_debug;
|
|
extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
|
|
__printflike(3,4);
|
|
#else
|
|
#define HALDEBUG(_ah, __m, _fmt, ...)
|
|
#endif /* AH_DEBUG */
|
|
|
|
/*
|
|
* Register logging definitions shared with ardecode.
|
|
*/
|
|
#include "ah_decode.h"
|
|
|
|
/*
|
|
* Common assertion interface. Note: it is a bad idea to generate
|
|
* an assertion failure for any recoverable event. Instead catch
|
|
* the violation and, if possible, fix it up or recover from it; either
|
|
* with an error return value or a diagnostic messages. System software
|
|
* does not panic unless the situation is hopeless.
|
|
*/
|
|
#ifdef AH_ASSERT
|
|
extern void ath_hal_assert_failed(const char* filename,
|
|
int lineno, const char* msg);
|
|
|
|
#define HALASSERT(_x) do { \
|
|
if (!(_x)) { \
|
|
ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
|
|
} \
|
|
} while (0)
|
|
#else
|
|
#define HALASSERT(_x)
|
|
#endif /* AH_ASSERT */
|
|
|
|
/*
|
|
* Regulatory domain support.
|
|
*/
|
|
|
|
/*
|
|
* Return the max allowed antenna gain and apply any regulatory
|
|
* domain specific changes.
|
|
*/
|
|
u_int ath_hal_getantennareduction(struct ath_hal *ah,
|
|
const struct ieee80211_channel *chan, u_int twiceGain);
|
|
|
|
/*
|
|
* Return the test group for the specific channel based on
|
|
* the current regulatory setup.
|
|
*/
|
|
u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
|
|
|
|
/*
|
|
* Map a public channel definition to the corresponding
|
|
* internal data structure. This implicitly specifies
|
|
* whether or not the specified channel is ok to use
|
|
* based on the current regulatory domain constraints.
|
|
*/
|
|
#ifndef AH_DEBUG
|
|
static OS_INLINE HAL_CHANNEL_INTERNAL *
|
|
ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
|
|
{
|
|
HAL_CHANNEL_INTERNAL *cc;
|
|
|
|
HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
|
|
cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
|
|
HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
|
|
return cc;
|
|
}
|
|
#else
|
|
/* NB: non-inline version that checks state */
|
|
HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
|
|
const struct ieee80211_channel *);
|
|
#endif /* AH_DEBUG */
|
|
|
|
/*
|
|
* Return the h/w frequency for a channel. This may be
|
|
* different from ic_freq if this is a GSM device that
|
|
* takes 2.4GHz frequencies and down-converts them.
|
|
*/
|
|
static OS_INLINE uint16_t
|
|
ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
|
|
{
|
|
return ath_hal_checkchannel(ah, c)->channel;
|
|
}
|
|
|
|
/*
|
|
* Convert between microseconds and core system clocks.
|
|
*/
|
|
extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
|
|
extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
|
|
|
|
/*
|
|
* Generic get/set capability support. Each chip overrides
|
|
* this routine to support chip-specific capabilities.
|
|
*/
|
|
extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
|
|
HAL_CAPABILITY_TYPE type, uint32_t capability,
|
|
uint32_t *result);
|
|
extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
|
|
HAL_CAPABILITY_TYPE type, uint32_t capability,
|
|
uint32_t setting, HAL_STATUS *status);
|
|
|
|
/*
|
|
* Diagnostic interface. This is an open-ended interface that
|
|
* is opaque to applications. Diagnostic programs use this to
|
|
* retrieve internal data structures, etc. There is no guarantee
|
|
* that calling conventions for calls other than HAL_DIAG_REVS
|
|
* are stable between HAL releases; a diagnostic application must
|
|
* use the HAL revision information to deal with ABI/API differences.
|
|
*
|
|
* NB: do not renumber these, certain codes are publicly used.
|
|
*/
|
|
enum {
|
|
HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */
|
|
HAL_DIAG_EEPROM = 1, /* EEPROM contents */
|
|
HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */
|
|
HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */
|
|
HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */
|
|
HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */
|
|
HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */
|
|
HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */
|
|
HAL_DIAG_ANI_STATS = 8, /* ANI statistics */
|
|
HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */
|
|
HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */
|
|
HAL_DIAG_PCDAC = 11, /* PCDAC table */
|
|
HAL_DIAG_TXRATES = 12, /* Transmit rate table */
|
|
HAL_DIAG_REGS = 13, /* Registers */
|
|
HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */
|
|
HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */
|
|
HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */
|
|
HAL_DIAG_EEREAD = 17, /* Read EEPROM word */
|
|
HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */
|
|
/* 19-26 removed, do not reuse */
|
|
HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */
|
|
HAL_DIAG_RDREAD = 28, /* Get regulatory domain */
|
|
HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */
|
|
HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */
|
|
HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */
|
|
HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
|
|
HAL_DIAG_SETREGS = 33, /* write registers */
|
|
};
|
|
|
|
enum {
|
|
HAL_BB_HANG_DFS = 0x0001,
|
|
HAL_BB_HANG_RIFS = 0x0002,
|
|
HAL_BB_HANG_RX_CLEAR = 0x0004,
|
|
HAL_BB_HANG_UNKNOWN = 0x0080,
|
|
|
|
HAL_MAC_HANG_SIG1 = 0x0100,
|
|
HAL_MAC_HANG_SIG2 = 0x0200,
|
|
HAL_MAC_HANG_UNKNOWN = 0x8000,
|
|
|
|
HAL_BB_HANGS = HAL_BB_HANG_DFS
|
|
| HAL_BB_HANG_RIFS
|
|
| HAL_BB_HANG_RX_CLEAR
|
|
| HAL_BB_HANG_UNKNOWN,
|
|
HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
|
|
| HAL_MAC_HANG_SIG2
|
|
| HAL_MAC_HANG_UNKNOWN,
|
|
};
|
|
|
|
/*
|
|
* Device revision information.
|
|
*/
|
|
typedef struct {
|
|
uint16_t ah_devid; /* PCI device ID */
|
|
uint16_t ah_subvendorid; /* PCI subvendor ID */
|
|
uint32_t ah_macVersion; /* MAC version id */
|
|
uint16_t ah_macRev; /* MAC revision */
|
|
uint16_t ah_phyRev; /* PHY revision */
|
|
uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
|
|
uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
|
|
} HAL_REVS;
|
|
|
|
/*
|
|
* Argument payload for HAL_DIAG_SETKEY.
|
|
*/
|
|
typedef struct {
|
|
HAL_KEYVAL dk_keyval;
|
|
uint16_t dk_keyix; /* key index */
|
|
uint8_t dk_mac[IEEE80211_ADDR_LEN];
|
|
int dk_xor; /* XOR key data */
|
|
} HAL_DIAG_KEYVAL;
|
|
|
|
/*
|
|
* Argument payload for HAL_DIAG_EEWRITE.
|
|
*/
|
|
typedef struct {
|
|
uint16_t ee_off; /* eeprom offset */
|
|
uint16_t ee_data; /* write data */
|
|
} HAL_DIAG_EEVAL;
|
|
|
|
|
|
typedef struct {
|
|
u_int offset; /* reg offset */
|
|
uint32_t val; /* reg value */
|
|
} HAL_DIAG_REGVAL;
|
|
|
|
/*
|
|
* 11n compatibility tweaks.
|
|
*/
|
|
#define HAL_DIAG_11N_SERVICES 0x00000003
|
|
#define HAL_DIAG_11N_SERVICES_S 0
|
|
#define HAL_DIAG_11N_TXSTOMP 0x0000000c
|
|
#define HAL_DIAG_11N_TXSTOMP_S 2
|
|
|
|
typedef struct {
|
|
int maxNoiseImmunityLevel; /* [0..4] */
|
|
int totalSizeDesired[5];
|
|
int coarseHigh[5];
|
|
int coarseLow[5];
|
|
int firpwr[5];
|
|
|
|
int maxSpurImmunityLevel; /* [0..7] */
|
|
int cycPwrThr1[8];
|
|
|
|
int maxFirstepLevel; /* [0..2] */
|
|
int firstep[3];
|
|
|
|
uint32_t ofdmTrigHigh;
|
|
uint32_t ofdmTrigLow;
|
|
int32_t cckTrigHigh;
|
|
int32_t cckTrigLow;
|
|
int32_t rssiThrLow;
|
|
int32_t rssiThrHigh;
|
|
|
|
int period; /* update listen period */
|
|
} HAL_ANI_PARAMS;
|
|
|
|
extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
|
|
const void *args, uint32_t argsize,
|
|
void **result, uint32_t *resultsize);
|
|
|
|
/*
|
|
* Setup a h/w rate table for use.
|
|
*/
|
|
extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
|
|
|
|
/*
|
|
* Common routine for implementing getChanNoise api.
|
|
*/
|
|
int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
|
|
|
|
/*
|
|
* Initialization support.
|
|
*/
|
|
typedef struct {
|
|
const uint32_t *data;
|
|
int rows, cols;
|
|
} HAL_INI_ARRAY;
|
|
|
|
#define HAL_INI_INIT(_ia, _data, _cols) do { \
|
|
(_ia)->data = (const uint32_t *)(_data); \
|
|
(_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
|
|
(_ia)->cols = (_cols); \
|
|
} while (0)
|
|
#define HAL_INI_VAL(_ia, _r, _c) \
|
|
((_ia)->data[((_r)*(_ia)->cols) + (_c)])
|
|
|
|
/*
|
|
* OS_DELAY() does a PIO READ on the PCI bus which allows
|
|
* other cards' DMA reads to complete in the middle of our reset.
|
|
*/
|
|
#define DMA_YIELD(x) do { \
|
|
if ((++(x) % 64) == 0) \
|
|
OS_DELAY(1); \
|
|
} while (0)
|
|
|
|
#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
|
|
int r; \
|
|
for (r = 0; r < N(regArray); r++) { \
|
|
OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
|
|
DMA_YIELD(regWr); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
|
|
int r; \
|
|
for (r = 0; r < N(regArray); r++) { \
|
|
OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
|
|
DMA_YIELD(regWr); \
|
|
} \
|
|
} while (0)
|
|
|
|
extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
|
|
int col, int regWr);
|
|
extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
|
|
int col);
|
|
extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
|
|
const uint32_t data[], int regWr);
|
|
|
|
#define CCK_SIFS_TIME 10
|
|
#define CCK_PREAMBLE_BITS 144
|
|
#define CCK_PLCP_BITS 48
|
|
|
|
#define OFDM_SIFS_TIME 16
|
|
#define OFDM_PREAMBLE_TIME 20
|
|
#define OFDM_PLCP_BITS 22
|
|
#define OFDM_SYMBOL_TIME 4
|
|
|
|
#define OFDM_HALF_SIFS_TIME 32
|
|
#define OFDM_HALF_PREAMBLE_TIME 40
|
|
#define OFDM_HALF_PLCP_BITS 22
|
|
#define OFDM_HALF_SYMBOL_TIME 8
|
|
|
|
#define OFDM_QUARTER_SIFS_TIME 64
|
|
#define OFDM_QUARTER_PREAMBLE_TIME 80
|
|
#define OFDM_QUARTER_PLCP_BITS 22
|
|
#define OFDM_QUARTER_SYMBOL_TIME 16
|
|
|
|
#define TURBO_SIFS_TIME 8
|
|
#define TURBO_PREAMBLE_TIME 14
|
|
#define TURBO_PLCP_BITS 22
|
|
#define TURBO_SYMBOL_TIME 4
|
|
|
|
#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
|
|
#endif /* _ATH_AH_INTERAL_H_ */
|