7bf5720a3f
These quirks are intended for optimizing CPU performance, not for applying errata workarounds. Nobody can expect that CPU with unfixed errata is stable enough to execute the kernel until quirks are applied. MFC after: 3 weeks
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*-
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUINFO_H_
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#define _MACHINE_CPUINFO_H_
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#include <sys/types.h>
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#define CPU_IMPLEMENTER_ARM 0x41
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#define CPU_IMPLEMENTER_QCOM 0x51
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#define CPU_IMPLEMENTER_MRVL 0x56
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/* ARM */
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#define CPU_ARCH_ARM1176 0xB76
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#define CPU_ARCH_CORTEX_A5 0xC05
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#define CPU_ARCH_CORTEX_A7 0xC07
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#define CPU_ARCH_CORTEX_A8 0xC08
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#define CPU_ARCH_CORTEX_A9 0xC09
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#define CPU_ARCH_CORTEX_A12 0xC0D
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#define CPU_ARCH_CORTEX_A15 0xC0F
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#define CPU_ARCH_CORTEX_A17 0xC11
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#define CPU_ARCH_CORTEX_A53 0xD03
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#define CPU_ARCH_CORTEX_A57 0xD07
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#define CPU_ARCH_CORTEX_A72 0xD08
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#define CPU_ARCH_CORTEX_A73 0xD09
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/* QCOM */
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#define CPU_ARCH_KRAIT_300 0x06F
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/* MRVL */
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#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */
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#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */
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struct cpuinfo {
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/* raw id registers */
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uint32_t midr;
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uint32_t ctr;
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uint32_t tcmtr;
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uint32_t tlbtr;
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uint32_t mpidr;
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uint32_t revidr;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t id_dfr0;
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uint32_t id_afr0;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_isar0;
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uint32_t id_isar1;
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uint32_t id_isar2;
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uint32_t id_isar3;
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uint32_t id_isar4;
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uint32_t id_isar5;
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uint32_t cbar;
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uint32_t ccsidr;
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uint32_t clidr;
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/* Parsed bits of above registers... */
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/* midr */
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int implementer;
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int revision;
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int architecture;
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int part_number;
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int patch;
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/* id_mmfr0 */
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int outermost_shareability;
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int shareability_levels;
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int auxiliary_registers;
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int innermost_shareability;
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/* id_mmfr1 */
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int mem_barrier;
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/* id_mmfr3 */
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int coherent_walk;
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int maintenance_broadcast;
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/* id_pfr1 */
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int generic_timer_ext;
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int virtualization_ext;
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int security_ext;
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/* L1 cache info */
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int dcache_line_size;
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int dcache_line_mask;
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int icache_line_size;
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int icache_line_mask;
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/* mpidr */
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int mp_ext;
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};
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extern struct cpuinfo cpuinfo;
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void cpuinfo_init(void);
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#if __ARM_ARCH >= 6
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void cpuinfo_reinit_mmu(uint32_t ttb);
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#endif
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#endif /* _MACHINE_CPUINFO_H_ */
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