155 lines
5.1 KiB
C
155 lines
5.1 KiB
C
/*-
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* Copyright (C) 2013 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _NTB_REGS_H_
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#define _NTB_REGS_H_
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#define NTB_LINK_ENABLE 0x0000
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#define NTB_LINK_DISABLE 0x0002
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#define NTB_LINK_STATUS_ACTIVE 0x2000
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#define NTB_LINK_SPEED_MASK 0x000f
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#define NTB_LINK_WIDTH_MASK 0x03f0
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#define XEON_MSIX_CNT 4
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#define XEON_MAX_SPADS 16
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#define XEON_MAX_COMPAT_SPADS 8
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/* Reserve the uppermost bit for link interrupt */
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#define XEON_MAX_DB_BITS 15
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#define XEON_DB_BITS_PER_VEC 5
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#define XEON_DB_HW_LINK 0x8000
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#define XEON_PCICMD_OFFSET 0x0504
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#define XEON_DEVCTRL_OFFSET 0x0598
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_PBAR2LMT_OFFSET 0x0000
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#define XEON_PBAR4LMT_OFFSET 0x0008
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#define XEON_PBAR2XLAT_OFFSET 0x0010
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#define XEON_PBAR4XLAT_OFFSET 0x0018
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#define XEON_SBAR2LMT_OFFSET 0x0020
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#define XEON_SBAR4LMT_OFFSET 0x0028
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#define XEON_SBAR2XLAT_OFFSET 0x0030
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#define XEON_SBAR4XLAT_OFFSET 0x0038
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#define XEON_SBAR0BASE_OFFSET 0x0040
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#define XEON_SBAR2BASE_OFFSET 0x0048
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#define XEON_SBAR4BASE_OFFSET 0x0050
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#define XEON_NTBCNTL_OFFSET 0x0058
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#define XEON_SBDF_OFFSET 0x005c
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#define XEON_PDOORBELL_OFFSET 0x0060
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#define XEON_PDBMSK_OFFSET 0x0062
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#define XEON_SDOORBELL_OFFSET 0x0064
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#define XEON_SDBMSK_OFFSET 0x0066
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#define XEON_USMEMMISS 0x0070
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#define XEON_SPAD_OFFSET 0x0080
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#define XEON_SPADSEMA4_OFFSET 0x00c0
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#define XEON_WCCNTRL_OFFSET 0x00e0
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#define XEON_B2B_SPAD_OFFSET 0x0100
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#define XEON_B2B_DOORBELL_OFFSET 0x0140
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#define XEON_B2B_XLAT_OFFSET 0x0144
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#define SOC_MSIX_CNT 34
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#define SOC_MAX_SPADS 16
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#define SOC_MAX_COMPAT_SPADS 16
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#define SOC_MAX_DB_BITS 34
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#define SOC_DB_BITS_PER_VEC 1
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#define SOC_PCICMD_OFFSET 0xb004
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#define SOC_MBAR23_OFFSET 0xb018
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#define SOC_MBAR45_OFFSET 0xb020
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#define SOC_DEVCTRL_OFFSET 0xb048
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#define SOC_LINK_STATUS_OFFSET 0xb052
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#define SOC_ERRCORSTS_OFFSET 0xb110
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#define SOC_SBAR2XLAT_OFFSET 0x0008
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#define SOC_SBAR4XLAT_OFFSET 0x0010
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#define SOC_PDOORBELL_OFFSET 0x0020
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#define SOC_PDBMSK_OFFSET 0x0028
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#define SOC_NTBCNTL_OFFSET 0x0060
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#define SOC_EBDF_OFFSET 0x0064
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#define SOC_SPAD_OFFSET 0x0080
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#define SOC_SPADSEMA_OFFSET 0x00c0
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#define SOC_STKYSPAD_OFFSET 0x00c4
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#define SOC_PBAR2XLAT_OFFSET 0x8008
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#define SOC_PBAR4XLAT_OFFSET 0x8010
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#define SOC_B2B_DOORBELL_OFFSET 0x8020
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#define SOC_B2B_SPAD_OFFSET 0x8080
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#define SOC_B2B_SPADSEMA_OFFSET 0x80c0
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#define SOC_B2B_STKYSPAD_OFFSET 0x80c4
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#define SOC_MODPHY_PCSREG4 0x1c004
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#define SOC_MODPHY_PCSREG6 0x1c006
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#define SOC_IP_BASE 0xc000
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#define SOC_DESKEWSTS_OFFSET (SOC_IP_BASE + 0x3024)
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#define SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180)
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#define SOC_LTSSMSTATEJMP_OFFSET (SOC_IP_BASE + 0x3040)
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#define SOC_IBSTERRRCRVSTS0_OFFSET (SOC_IP_BASE + 0x3324)
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#define SOC_DESKEWSTS_DBERR (1 << 15)
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#define SOC_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
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#define SOC_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
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#define SOC_IBIST_ERR_OFLOW 0x7fff7fff
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#define NTB_CNTL_BAR23_SNOOP (1 << 2)
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#define NTB_CNTL_BAR45_SNOOP (1 << 6)
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#define SOC_CNTL_LINK_DOWN (1 << 16)
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#define XEON_PBAR23SZ_OFFSET 0x00d0
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#define XEON_PBAR45SZ_OFFSET 0x00d1
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#define NTB_PPD_OFFSET 0x00d4
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#define XEON_PPD_CONN_TYPE 0x0003
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#define XEON_PPD_DEV_TYPE 0x0010
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#define SOC_PPD_INIT_LINK 0x0008
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#define SOC_PPD_CONN_TYPE 0x0300
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#define SOC_PPD_DEV_TYPE 0x1000
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#define NTB_CONN_CLASSIC 0
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#define NTB_CONN_B2B 1
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#define NTB_CONN_RP 2
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#define NTB_DEV_DSD 1
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#define NTB_DEV_USD 0
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#define PBAR2XLAT_USD_ADDR 0x0000004000000000
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#define PBAR4XLAT_USD_ADDR 0x0000008000000000
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#define MBAR01_USD_ADDR 0x000000210000000c
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#define MBAR23_USD_ADDR 0x000000410000000c
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#define MBAR45_USD_ADDR 0x000000810000000c
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#define PBAR2XLAT_DSD_ADDR 0x0000004100000000
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#define PBAR4XLAT_DSD_ADDR 0x0000008100000000
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#define MBAR01_DSD_ADDR 0x000000200000000c
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#define MBAR23_DSD_ADDR 0x000000400000000c
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#define MBAR45_DSD_ADDR 0x000000800000000c
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/* XEON Shadowed MMIO Space */
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#define XEON_SHADOW_PDOORBELL_OFFSET 0x60
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#define XEON_SHADOW_SPAD_OFFSET 0x80
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#endif /* _NTB_REGS_H_ */
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