0050ea2415
Re-implement clocks for these SoC by using now standard extres/clk framework. This is necessary for future expansion of these. The new implementation is (due to the size of the patch) only the initial (minimum) version. It will be updated/expanded with a subsequent set of particular patches. This patch is also not tested on OMAP4 based boards (BeagleBone), so all possible issues should be (and will be) fixed by ASAP once identified. Submited by: Oskar Holmlund (oskar.holmlund@ohdata.se) Differential Revision: https://reviews.freebsd.org/D25118
265 lines
6.9 KiB
C
265 lines
6.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/libkern.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clock_common.h"
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#if 0
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#define DPRINTF(dev, msg...) device_printf(dev, msg)
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#else
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#define DPRINTF(dev, msg...)
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#endif
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/*
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* Devicetree description
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* Documentation/devicetree/bindings/clock/ti/divider.txt
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*/
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struct ti_divider_softc {
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device_t sc_dev;
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bool attach_done;
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struct clk_div_def div_def;
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struct clock_cell_info clock_cell;
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struct clkdom *clkdom;
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};
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static int ti_divider_probe(device_t dev);
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static int ti_divider_attach(device_t dev);
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static int ti_divider_detach(device_t dev);
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#define TI_DIVIDER_CLOCK 2
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#define TI_COMPOSITE_DIVIDER_CLOCK 1
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#define TI_DIVIDER_END 0
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static struct ofw_compat_data compat_data[] = {
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{ "ti,divider-clock", TI_DIVIDER_CLOCK },
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{ "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },
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{ NULL, TI_DIVIDER_END }
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};
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static int
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register_clk(struct ti_divider_softc *sc) {
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int err;
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sc->clkdom = clkdom_create(sc->sc_dev);
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if (sc->clkdom == NULL) {
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DPRINTF(sc->sc_dev, "Failed to create clkdom\n");
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return (ENXIO);
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}
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err = clknode_div_register(sc->clkdom, &sc->div_def);
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if (err) {
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DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err);
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return (ENXIO);
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}
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err = clkdom_finit(sc->clkdom);
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if (err) {
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DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);
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return (ENXIO);
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}
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return (0);
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}
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static int
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ti_divider_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "TI Divider Clock");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ti_divider_attach(device_t dev)
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{
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struct ti_divider_softc *sc;
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phandle_t node;
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int err;
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cell_t value;
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uint32_t ti_max_div;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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node = ofw_bus_get_node(dev);
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/* Grab the content of reg properties */
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OF_getencprop(node, "reg", &value, sizeof(value));
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sc->div_def.offset = value;
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if (OF_hasprop(node, "ti,bit-shift")) {
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OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));
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sc->div_def.i_shift = value;
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}
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if (OF_hasprop(node, "ti,index-starts-at-one")) {
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sc->div_def.div_flags = CLK_DIV_ZERO_BASED;
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}
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if (OF_hasprop(node, "ti,index-power-of-two")) {
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/* FIXME: later */
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device_printf(sc->sc_dev, "ti,index-power-of-two - Not implemented\n");
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/* remember to update i_width a few lines below */
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}
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if (OF_hasprop(node, "ti,max-div")) {
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OF_getencprop(node, "ti,max-div", &value, sizeof(value));
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ti_max_div = value;
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}
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if (OF_hasprop(node, "clock-output-names"))
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device_printf(sc->sc_dev, "clock-output-names\n");
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if (OF_hasprop(node, "ti,dividers"))
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device_printf(sc->sc_dev, "ti,dividers\n");
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if (OF_hasprop(node, "ti,min-div"))
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device_printf(sc->sc_dev, "ti,min-div - Not implemented\n");
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if (OF_hasprop(node, "ti,autoidle-shift"))
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device_printf(sc->sc_dev, "ti,autoidle-shift - Not implemented\n");
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if (OF_hasprop(node, "ti,set-rate-parent"))
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device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");
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if (OF_hasprop(node, "ti,latch-bit"))
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device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");
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/* Figure out the width from ti_max_div */
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if (sc->div_def.div_flags)
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sc->div_def.i_width = fls(ti_max_div-1);
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else
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sc->div_def.i_width = fls(ti_max_div);
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DPRINTF(sc->sc_dev, "div_def.i_width %x\n", sc->div_def.i_width);
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read_clock_cells(sc->sc_dev, &sc->clock_cell);
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create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);
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err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);
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if (err) {
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/* free_clkdef will be called in ti_divider_new_pass */
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DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");
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return (bus_generic_attach(sc->sc_dev));
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}
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err = register_clk(sc);
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if (err) {
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/* free_clkdef will be called in ti_divider_new_pass */
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DPRINTF(sc->sc_dev, "register_clk failed\n");
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return (bus_generic_attach(sc->sc_dev));
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}
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sc->attach_done = true;
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free_clkdef(&sc->div_def.clkdef);
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return (bus_generic_attach(sc->sc_dev));
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}
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static int
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ti_divider_detach(device_t dev)
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{
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return (EBUSY);
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}
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static void
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ti_divider_new_pass(device_t dev)
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{
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struct ti_divider_softc *sc;
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int err;
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sc = device_get_softc(dev);
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if (sc->attach_done) {
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return;
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}
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err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);
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if (err) {
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/* free_clkdef will be called in a later call to ti_divider_new_pass */
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DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n");
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return;
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}
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err = register_clk(sc);
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if (err) {
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/* free_clkdef will be called in a later call to ti_divider_new_pass */
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DPRINTF(sc->sc_dev, "new_pass register_clk failed\n");
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return;
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}
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sc->attach_done = true;
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free_clkdef(&sc->div_def.clkdef);
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}
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static device_method_t ti_divider_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ti_divider_probe),
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DEVMETHOD(device_attach, ti_divider_attach),
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DEVMETHOD(device_detach, ti_divider_detach),
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/* Bus interface */
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DEVMETHOD(bus_new_pass, ti_divider_new_pass),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(ti_divider, ti_divider_driver, ti_divider_methods,
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sizeof(struct ti_divider_softc));
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static devclass_t ti_divider_devclass;
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EARLY_DRIVER_MODULE(ti_divider, simplebus, ti_divider_driver,
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ti_divider_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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MODULE_VERSION(ti_divider, 1);
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