f36cfd49ad
license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson. Approved by: core, peter, alc, rwatson
105 lines
4.2 KiB
C
105 lines
4.2 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* modified for PC9801 by M.Ishii
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* Kyoto University Microcomputer Club (KMC)
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*/
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/*
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* modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
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*/
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/* define command and status code */
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#define CMD8251_TxEN 0x01 /* transmit enable */
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#define CMD8251_DTR 0x02 /* assert DTR */
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#define CMD8251_RxEN 0x04 /* receive enable */
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#define CMD8251_SBRK 0x08 /* send break */
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#define CMD8251_ER 0x10 /* error reset */
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#define CMD8251_RTS 0x20 /* assert RTS */
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#define CMD8251_RESET 0x40 /* internal reset */
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#define CMD8251_EH 0x80 /* enter hunt mode (only synchronous mode)*/
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#define STS8251_TxRDY 0x01 /* transmit READY */
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#define STS8251_RxRDY 0x02 /* data exists in receive buffer */
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#define STS8251_TxEMP 0x04 /* transmit buffer EMPTY */
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#define STS8251_PE 0x08 /* perity error */
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#define STS8251_OE 0x10 /* overrun error */
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#define STS8251_FE 0x20 /* framing error */
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#define STS8251_BD_SD 0x40 /* break detect (async) / sync detect (sync) */
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#define STS8251_DSR 0x80 /* DSR is asserted */
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#define STS8251F_TxEMP 0x01 /* transmit buffer EMPTY */
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#define STS8251F_TxRDY 0x02 /* transmit READY */
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#define STS8251F_RxRDY 0x04 /* data exists in receive buffer */
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#define STS8251F_OE 0x10 /* overrun error */
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#define STS8251F_PE 0x20 /* perity error */
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#define STS8251F_BD_SD 0x80 /* break detect (async) / sync detect (sync) */
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#define INTR8251F_DTCT 0x60 /* FIFO detection mask */
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#define INTR8251F_INTRV 0x0e /* interrupt event */
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#define INTR8251F_TO 0x0c /* receive timeout */
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#define INTR8251F_LSTS 0x06 /* line status */
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#define INTR8251F_RxRDY 0x04 /* receive READY */
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#define INTR8251F_TxRDY 0x02 /* transmit READY */
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#define INTR8251F_ISEV 0x01 /* event occured */
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#define INTR8251F_MSTS 0x00 /* modem status */
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#define CTRL8251F_ENABLE 0x01 /* enable FIFO */
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#define CTRL8251F_RCV_RST 0x02 /* reset receive FIFO */
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#define CTRL8251F_XMT_RST 0x04 /* reset transmit FIFO */
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#define MOD8251_5BITS 0x00
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#define MOD8251_6BITS 0x04
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#define MOD8251_7BITS 0x08
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#define MOD8251_8BITS 0x0c
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#define MOD8251_PDISAB 0x00 /* parity disable */
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#define MOD8251_PODD 0x10 /* parity odd */
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#define MOD8251_PEVEN 0x30 /* parity even */
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#define MOD8251_STOP1 0x40 /* stop bit len = 1bit */
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#define MOD8251_STOP2 0xc0 /* stop bit len = 2bit */
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#define MOD8251_CLKX16 0x02 /* x16 */
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#define MOD8251_CLKX1 0x01 /* x1 */
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#define CICSCD_CD 0x20 /* CD */
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#define CICSCD_CS 0x40 /* CS */
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#define CICSCD_CI 0x80 /* CI */
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#define CICSCDF_CS 0x10 /* CS */
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#define CICSCDF_DR 0x20 /* DR */
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#define CICSCDF_CI 0x40 /* CI */
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#define CICSCDF_CD 0x80 /* CD */
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/* interrupt mask control */
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#define IEN_Rx 0x01
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#define IEN_TxEMP 0x02
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#define IEN_Tx 0x04
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