449 lines
10 KiB
C
449 lines
10 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/param.h> /* XXX trim includes */
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/md_var.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <isa/isavar.h>
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#include <machine/nexusvar.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/segments.h>
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#include <machine/pc/bios.h>
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#include "pcib_if.h"
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static struct PIR_entry *pci_route_table;
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static int pci_route_count;
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/*
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* Initialise access to PCI configuration space
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*/
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int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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u_long sigaddr;
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static struct PIR_table *pt;
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u_int8_t ck, *cv;
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int i;
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if (opened)
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return(1);
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if (pcibios_cfgopen() != 0) {
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usebios = 1;
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} else if (pcireg_cfgopen() != 0) {
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usebios = 0;
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} else {
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return(0);
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}
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/*
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* Look for the interrupt routing table.
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*/
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/* XXX use PCI BIOS if it's available */
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if ((pt == NULL) && ((sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0)) != 0)) {
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pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
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for (cv = (u_int8_t *)pt, ck = 0, i = 0; i < (pt->pt_header.ph_length); i++) {
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ck += cv[i];
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}
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if (ck == 0) {
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pci_route_table = &pt->pt_entry[0];
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pci_route_count = (pt->pt_header.ph_length - sizeof(struct PIR_header)) / sizeof(struct PIR_entry);
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printf("Using $PIR table, %d entries at %p\n", pci_route_count, pci_route_table);
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}
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}
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opened = 1;
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return(1);
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}
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/*
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* Read configuration space register
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*/
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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return(usebios ?
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
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}
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/*
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* Route a PCI interrupt
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*
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* XXX this needs to learn to actually route uninitialised interrupts as well
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* as just returning interrupts for stuff that's already initialised.
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*/
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int
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pci_cfgintr(int bus, int device, int pin)
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{
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struct PIR_entry *pe;
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int i;
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if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
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(pin < 1) || (pin > 4))
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return(255);
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/*
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* Scan the entry table for a contender
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*/
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for (i = 0, pe = pci_route_table; i < pci_route_count; i++, pe++) {
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if ((bus != pe->pe_bus) || (device != pe->pe_device))
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continue;
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if (!powerof2(pe->pe_intpin[pin - 1].irqs)) {
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printf("pci_cfgintr: %d:%d:%c is not routed to a unique interrupt\n", bus, device, 'A' + pin - 1);
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break;
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}
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printf("pci_cfgintr: %d:%d:%c routed to irq %d\n", bus, device, 'A' + pin - 1, ffs(pe->pe_intpin[pin - 1].irqs));
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return(ffs(pe->pe_intpin[pin - 1].irqs));
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}
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return(255);
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}
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/*
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* Config space access using BIOS functions
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*/
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static int
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pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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struct bios_regs args;
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u_int mask;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_READ_CONFIG_BYTE;
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mask = 0xff;
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break;
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case 2:
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args.eax = PCIBIOS_READ_CONFIG_WORD;
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mask = 0xffff;
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break;
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case 4:
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args.eax = PCIBIOS_READ_CONFIG_DWORD;
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mask = 0xffffffff;
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break;
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default:
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return(-1);
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}
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args.ebx = (bus << 8) | (slot << 3) | func;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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/* check call results? */
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return(args.ecx & mask);
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}
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static void
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pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_WRITE_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
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break;
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default:
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return;
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}
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args.ebx = (bus << 8) | (slot << 3) | func;
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args.ecx = data;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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/*
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* Determine whether there is a PCI BIOS present
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*/
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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}
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/*
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* Configuration space access using direct register operations
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*/
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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}
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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}
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/* check whether the configuration mechanism has been correctly identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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u_char device;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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unsigned id, class, header;
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if (bootverbose)
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printf("%d ", device);
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id = inl(pci_cfgenable(0, device, 0, 0, 4));
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if (id == 0 || id == -1)
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continue;
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class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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header = inb(pci_cfgenable(0, device, 0, 14, 1));
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pcireg_cfgopen(void)
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{
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unsigned long mode1res,oldval1;
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unsigned char mode2res,oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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outb(CONF1_ADDR_PORT +3, 0);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = 0;
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devmax = 0;
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return (cfgmech);
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}
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