120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/*-
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* Copyright (c) 2013 Thomas Skibo. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <arm/xilinx/zy7_reg.h>
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#define ZYNQ7_CPU1_ENTRY 0xfffffff0
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#define SCU_CONTROL_REG 0xf8f00000
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#define SCU_CONTROL_ENABLE (1 << 0)
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void
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platform_mp_init_secondary(void)
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{
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arm_init_secondary_ic();
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}
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void
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platform_mp_setmaxid(void)
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{
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mp_maxid = 1;
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}
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int
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platform_mp_probe(void)
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{
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mp_ncpus = 2;
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return (1);
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}
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void
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platform_mp_start_ap(void)
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{
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bus_space_handle_t scu_handle;
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bus_space_handle_t ocm_handle;
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uint32_t scu_ctrl;
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/* Map in SCU control register. */
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if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
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0, &scu_handle) != 0)
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panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
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/* Set SCU enable bit. */
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scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
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scu_ctrl |= SCU_CONTROL_ENABLE;
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bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
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bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
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/* Map in magic location to give entry address to CPU1. */
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if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
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0, &ocm_handle) != 0)
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panic("platform_mp_start_ap: Couldn't map OCM\n");
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/* Write start address for CPU1. */
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bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
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pmap_kextract((vm_offset_t)mpentry));
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bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
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/*
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* The SCU is enabled above but I think the second CPU doesn't
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* turn on filtering until after the wake-up below. I think that's why
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* things don't work if I don't put these cache ops here. Also, the
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* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
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* needs a write-back too.
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*/
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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/* Wake up CPU1. */
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armv7_sev();
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}
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void
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platform_ipi_send(cpuset_t cpus, u_int ipi)
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{
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pic_ipi_send(cpus, ipi);
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}
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