b8821f8415
On armv4 these are defined as synonyms right now, but it's a bit ambiguous what NOCACHE means (is buffering/write-combining also enabled or not?); this is a first step towards replacing PTE_NOCACHE with a less ambiguous name.
405 lines
12 KiB
C
405 lines
12 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* machdep.c
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*
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* Machine dependant functions for kernel setup
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*
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* This file needs a lot of work.
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*
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* Created : 17/09/94
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*/
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#include "opt_ddb.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/cons.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/buf.h>
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#include <sys/exec.h>
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#include <sys/kdb.h>
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#include <sys/msgbuf.h>
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#include <machine/physmem.h>
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#include <machine/reg.h>
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#include <machine/cpu.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <machine/devmap.h>
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#include <machine/vmparam.h>
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#include <machine/pcb.h>
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#include <machine/undefined.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <sys/reboot.h>
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#include <arm/s3c2xx0/s3c24x0var.h>
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#include <arm/s3c2xx0/s3c2410reg.h>
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#include <arm/s3c2xx0/s3c2xx0board.h>
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/* Page table for mapping proc0 zero page */
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#define KERNEL_PT_SYS 0
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#define KERNEL_PT_KERN 1
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#define KERNEL_PT_KERN_NUM 44
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/* L2 table for mapping after kernel */
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#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
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#define KERNEL_PT_AFKERNEL_NUM 5
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/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
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#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
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extern int s3c2410_pclk;
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struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
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/* Physical and virtual addresses for some global pages */
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struct pv_addr systempage;
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struct pv_addr msgbufpv;
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struct pv_addr irqstack;
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struct pv_addr undstack;
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struct pv_addr abtstack;
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struct pv_addr kernelstack;
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#define _A(a) ((a) & ~L1_S_OFFSET)
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#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
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/* Static device mappings. */
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static const struct arm_devmap_entry s3c24x0_devmap[] = {
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/*
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* Map the devices we need early on.
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*/
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{
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_A(S3C24X0_CLKMAN_BASE),
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_A(S3C24X0_CLKMAN_PA_BASE),
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_S(S3C24X0_CLKMAN_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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_A(S3C24X0_GPIO_BASE),
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_A(S3C24X0_GPIO_PA_BASE),
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_S(S3C2410_GPIO_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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_A(S3C24X0_INTCTL_BASE),
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_A(S3C24X0_INTCTL_PA_BASE),
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_S(S3C24X0_INTCTL_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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_A(S3C24X0_TIMER_BASE),
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_A(S3C24X0_TIMER_PA_BASE),
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_S(S3C24X0_TIMER_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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_A(S3C24X0_UART0_BASE),
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_A(S3C24X0_UART0_PA_BASE),
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_S(S3C24X0_UART_PA_BASE(3) - S3C24X0_UART0_PA_BASE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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_A(S3C24X0_WDT_BASE),
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_A(S3C24X0_WDT_PA_BASE),
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_S(S3C24X0_WDT_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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0,
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0,
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0,
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0,
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0,
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}
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};
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#undef _A
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#undef _S
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#define ioreg_read32(a) (*(volatile uint32_t *)(a))
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#define ioreg_write32(a,v) (*(volatile uint32_t *)(a)=(v))
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struct arm32_dma_range s3c24x0_range = {
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.dr_sysbase = 0,
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.dr_busbase = 0,
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.dr_len = 0,
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};
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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if (s3c24x0_range.dr_len == 0) {
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s3c24x0_range.dr_sysbase = dump_avail[0];
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s3c24x0_range.dr_busbase = dump_avail[0];
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s3c24x0_range.dr_len = dump_avail[1] - dump_avail[0];
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}
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return (&s3c24x0_range);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (1);
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}
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void *
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initarm(struct arm_boot_params *abp)
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{
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struct pv_addr kernel_l1pt;
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int loop;
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u_int l1pagetable;
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vm_offset_t freemempos;
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vm_offset_t afterkern;
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vm_offset_t lastaddr;
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int i;
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uint32_t memsize;
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boothowto = 0; /* Likely not needed */
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lastaddr = parse_boot_param(abp);
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arm_physmem_kernaddr = abp->abp_physaddr;
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i = 0;
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set_cpufuncs();
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cpufuncs.cf_sleep = s3c24x0_sleep;
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pcpu0_init();
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/* Do basic tuning, hz etc */
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init_param1();
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#define KERNEL_TEXT_BASE (KERNBASE)
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freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
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/* Define a macro to simplify memory allocation */
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#define valloc_pages(var, np) \
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alloc_pages((var).pv_va, (np)); \
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(var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
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#define alloc_pages(var, np) \
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(var) = freemempos; \
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freemempos += (np * PAGE_SIZE); \
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memset((char *)(var), 0, ((np) * PAGE_SIZE));
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while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
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freemempos += PAGE_SIZE;
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valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
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valloc_pages(kernel_pt_table[loop],
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L2_TABLE_SIZE / PAGE_SIZE);
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} else {
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kernel_pt_table[loop].pv_va = freemempos -
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(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
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L2_TABLE_SIZE_REAL;
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kernel_pt_table[loop].pv_pa =
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kernel_pt_table[loop].pv_va - KERNVIRTADDR +
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abp->abp_physaddr;
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}
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}
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/*
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* Allocate a page for the system page mapped to V0x00000000
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* This page will just contain the system vectors and can be
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* shared by all processes.
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*/
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valloc_pages(systempage, 1);
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/* Allocate stacks for all modes */
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valloc_pages(irqstack, IRQ_STACK_SIZE);
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valloc_pages(abtstack, ABT_STACK_SIZE);
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valloc_pages(undstack, UND_STACK_SIZE);
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valloc_pages(kernelstack, KSTACK_PAGES);
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valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
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/*
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* Now we start construction of the L1 page table
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* We start by mapping the L2 page tables into the L1.
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* This means that we can replace L1 mappings later on if necessary
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*/
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l1pagetable = kernel_l1pt.pv_va;
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/* Map the L2 pages tables in the L1 page table */
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pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
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&kernel_pt_table[KERNEL_PT_SYS]);
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for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
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pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
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&kernel_pt_table[KERNEL_PT_KERN + i]);
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pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
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(((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
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- 1));
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for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
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pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
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&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
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}
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/* Map the vector page. */
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pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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/* Map the stack pages */
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pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
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IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
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ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
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UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
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KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
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L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
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msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
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kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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}
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arm_devmap_bootstrap(l1pagetable, s3c24x0_devmap);
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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setttb(kernel_l1pt.pv_pa);
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cpu_tlb_flushID();
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cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
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/*
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* Pages were allocated during the secondary bootstrap for the
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* stacks for different CPU modes.
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* We must now set the r13 registers in the different CPU modes to
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* point to these stacks.
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* Since the ARM stacks use STMFD etc. we must set r13 to the top end
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* of the stack memory.
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*/
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cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
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set_stackptrs(0);
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/*
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* We must now clean the cache again....
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* Cleaning may be done by reading new data to displace any
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* dirty data in the cache. This will have happened in setttb()
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* but since we are boot strapping the addresses used for the read
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* may have just been remapped and thus the cache could be out
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* of sync. A re-clean after the switch will cure this.
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* After booting there are no gross relocations of the kernel thus
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* this problem will not occur after initarm().
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*/
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cpu_idcache_wbinv_all();
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cpu_setup("");
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/* Disable all peripheral interrupts */
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ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0);
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memsize = board_init();
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/* Find pclk for uart */
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switch(ioreg_read32(S3C24X0_GPIO_BASE + GPIO_GSTATUS1) >> 16) {
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case 0x3241:
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s3c2410_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
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&s3c2410_pclk);
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break;
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case 0x3244:
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s3c2440_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
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&s3c2410_pclk);
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break;
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}
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cninit();
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undefined_init();
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init_proc0(kernelstack.pv_va);
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arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
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pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
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vm_max_kernel_address = KERNVIRTADDR + 3 * memsize;
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pmap_bootstrap(freemempos, &kernel_l1pt);
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msgbufp = (void*)msgbufpv.pv_va;
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msgbufinit(msgbufp, msgbufsize);
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mutex_init();
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/*
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* Add the physical ram we have available.
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*
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* Exclude the kernel, and all the things we allocated which immediately
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* follow the kernel, from the VM allocation pool but not from crash
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* dumps. virtual_avail is a global variable which tracks the kva we've
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* "allocated" while setting up pmaps.
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*
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* Prepare the list of physical memory available to the vm subsystem.
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*/
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arm_physmem_hardware_region(PHYSADDR, memsize);
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arm_physmem_exclude_region(abp->abp_physaddr,
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virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
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arm_physmem_init_kernel_globals();
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init_param2(physmem);
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kdb_init();
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return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
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sizeof(struct pcb)));
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}
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