Ruslan Bukin ca20f8ec29 o Replace __riscv__ with __riscv ... o Replace __riscv64 with (__riscv && __riscv_xlen == 64) This is required to support new GCC 7.1 compiler. This is compatible with current GCC 6.1 compiler. RISC-V is extensible ISA and the idea here is to have built-in define per each extension, so together with __riscv we will have some subset of these as well (depending on -march string passed to compiler): __riscv_compressed __riscv_atomic __riscv_mul __riscv_div __riscv_muldiv __riscv_fdiv __riscv_fsqrt __riscv_float_abi_soft __riscv_float_abi_single __riscv_float_abi_double __riscv_cmodel_medlow __riscv_cmodel_medany __riscv_cmodel_pic __riscv_xlen Reviewed by: ngie Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11901		2017-08-07 14:09:57 +00:00
..
aarch64	First cut of DTrace for AArch64.	2015-07-01 15:51:11 +00:00
arm	Initial version of DTrace on ARM32.	2015-02-10 19:41:30 +00:00
common	o Replace __riscv__ with __riscv	2017-08-07 14:09:57 +00:00
intel	Fix an off-by-one in an assertion on fasttrap tracepoint sizes.	2017-01-27 17:58:41 +00:00
mips
powerpc	Move implementations of uread() and uwrite() to the illumos compat layer.	2016-09-24 21:40:14 +00:00
riscv	Add initial DTrace support for RISC-V.	2016-05-24 16:41:37 +00:00