219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
465 lines
20 KiB
C
465 lines
20 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
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*
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* This software file (the "File") is owned and distributed by Cavium
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* Networks ("Cavium") under the following dual licensing option: The dual
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* licensing option gives you, the licensee, the choice between the following
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* alternative licensing terms. Once you have made an election to use the
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* File under one of the following alternative licensing terms (license
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* types) you are bound by the respective terms and you may distribute the
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* file (or any derivative thereof), to the extent allowed by the respective
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* licensing term, only if you (i) delete this introductory statement
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* regarding the dual licensing option from the file you will distribute,
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* (ii) delete the licensing term that you have elected NOT to use from the
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* file you will distribute and (iii) follow the respective licensing term
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* that you have elected to use with respect to the correct attribution or
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* licensing term that you have to include with your distribution.
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*
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* ***
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* OCTEON SDK License Type 2:
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*
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* IMPORTANT: Read this Agreement carefully before clicking on the "I accept"
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* button to download the Software and/or before using the Software. This
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* License Agreement (the "Agreement") is a legal agreement between you,
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* either an individual or a single legal entity ("You" or "you"), and Cavium
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* software that can be downloaded after accepting this Agreement and/or that
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* terms of this Agreement before downloading and/or using the Software. By
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* clicking on the "I accept" button to download and/or by using the
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* Software, you are indicating that you have read and understood, and assent
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* to be bound by, the terms of this Agreement. If you do not agree to the
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* terms of the Agreement, you are not granted any rights whatsoever in the
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* Software. If you are not willing to be bound by these terms and
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* conditions, you should not use or cease all use of the Software. This
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* Software is the property of Cavium Networks and constitutes the
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* proprietary information of Cavium Networks. You agree to take reasonable
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* steps to prevent the disclosure, unauthorized use or unauthorized
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* distribution of the Software to any third party.
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*
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* License Grant. Subject to the terms and conditions of this Agreement,
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* and royalty-free license to
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* modifications of this Agreement must be in writing and agreed to by both
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* parties.
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*
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* Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
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*
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* ***
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*
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* OCTEON SDK License Type 4:
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*
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2007 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as published by
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* the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
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* See the GNU General Public License for more details.
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* it under the terms of the GNU General Public License, Version 2, as published by
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* the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* This code is an example of using twsi core in raw mode, bypasing High
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* Level Controller (HLC). It is recommended to use HLC if only possible as
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* it is more efficient and robust mechanism.
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* The example code shows use of twsi for generating long (more that 8 bytes HLC limit)
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* read - write transactions using 7-bit addressing. Different types of
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* transactions can be generated if needed. Make sure that commands written to twsi core
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* follow core state transitions outlinged in OCTEON documentation. The core state is
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* reported in stat register after the command colpletion. In each state core will accept
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* only the allowed commands.
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*/
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#include <stdio.h>
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#include <cvmx.h>
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#include <cvmx-csr-typedefs.h>
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#include "cvmx-twsi-raw.h"
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/*
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* uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
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* twsi core register read
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* twsi_id - twsi core index
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* reg 0 - 8-bit register
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* returns 8-bit register contetn
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*/
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uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
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{
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cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
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sw_twsi_val.u64 = 0;
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sw_twsi_val.s.v = 1;
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sw_twsi_val.s.op = 6;
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sw_twsi_val.s.eop_ia = reg;
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sw_twsi_val.s.r = 1;
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
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;
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return sw_twsi_val.s.d ;
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}
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/*
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* uint8_t cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
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*
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* twsi core register write
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* twsi_id - twsi core index
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* reg 0 - 8-bit register
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* data - data to write
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* returns 0;
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*/
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int cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
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{
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cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
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sw_twsi_val.u64 = 0;
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sw_twsi_val.s.v = 1;
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sw_twsi_val.s.op = 6;
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sw_twsi_val.s.eop_ia = reg;
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sw_twsi_val.s.d = data;
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
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;
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return 0;
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}
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/*
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* cvmx_twsi_wait_iflg(int twsi_id)
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* cvmx_twsi_wait_stop(int twsi_id)
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*
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* Helper functions.
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* Busy wait for interrupt flag or stop bit on control register. This implementation is for OS-less
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* application. With OS services available it could be implemented with semaphore
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* block and interrupt wake up.
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* TWSI_WAIT for loop must be defined large enough to allow on-wire transaction to finish - that is
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* about 10 twsi clocks
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*/
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#define TWSI_WAIT 10000000
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static inline int cvmx_twsi_wait_iflg(int twsi_id)
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{
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octeon_twsi_ctl_t ctl_reg;
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int wait = TWSI_WAIT;
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do{
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ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
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} while((ctl_reg.s.iflg ==0) && (wait-- >0));
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if(wait == 0) return -1;
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return 0;
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}
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static inline int cvmx_twsi_wait_stop(int twsi_id)
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{
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octeon_twsi_ctl_t ctl_reg;
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int wait = TWSI_WAIT;
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do{
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ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
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} while((ctl_reg.s.stp ==1) && (wait-- >0));
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if(wait == 0) return -1;
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return 0;
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}
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/*
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* uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
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* uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
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*
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* helper functions - read or write byte to data reg and reads the TWSI core status
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*/
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static uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
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{
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octeon_twsi_ctl_t ctl_reg;
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octeon_twsi_data_t data;
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octeon_twsi_stat_t stat;
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/* clear interrupt flag, set aak for requested ACK signal level */
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ctl_reg.u8 =0;
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ctl_reg.s.aak = (ack==0) ?0:1;
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ctl_reg.s.enab =1;
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cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
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/* wait for twsi_ctl[iflg] to be set */
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if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
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/* read the byte */
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data.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_DATA_REG);
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*byte = data.s.data;
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error:
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/* read the status */
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stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
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return stat.s.stat;
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}
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static uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
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{
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octeon_twsi_ctl_t ctl_reg;
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octeon_twsi_data_t data;
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octeon_twsi_stat_t stat;
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/* tx data byte - write to twsi_data reg, then clear twsi_ctl[iflg] */
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data.s.data = byte;
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cvmx_twsix_write_ctr(twsi_id, TWSI_DATA_REG, data.u8);
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ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
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ctl_reg.s.iflg =0;
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cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
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/* wait for twsi_ctl[iflg] to be set */
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if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
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error:
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/* read the status */
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stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
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return stat.s.stat;
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}
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/*
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* int octeon_i2c_xfer_msg_raw(struct i2c_msg *msg)
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*
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* Send (read or write) a message with 7-bit address device over direct control of
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* TWSI core, bypassind HLC. Will try to finish the transaction on failure, so core state
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* expected to be idle with HLC enabled on exit.
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*
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* dev - TWSI controller index (0 for cores with single controler)
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* msg - message to transfer
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* returns 0 on success, TWSI core state on error. Will try to finish the transaction on failure, so core state expected to be idle
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*/
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int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg)
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{
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int i =0;
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octeon_twsi_ctl_t ctl_reg;
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octeon_twsi_addr_t addr;
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octeon_twsi_stat_t stat;
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int is_read = msg->flags & I2C_M_RD;
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int ret =0;
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/* check the core state, quit if not idle */
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stat.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
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if(stat.s.stat != TWSI_IDLE) {
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msg->len =0; return stat.s.stat;
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}
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/* first send start - set twsi_ctl[sta] to 1 */
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ctl_reg.u8 =0;
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ctl_reg.s.enab =1;
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ctl_reg.s.sta =1;
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ctl_reg.s.iflg =0;
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cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
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/* wait for twsi_ctl[iflg] to be set */
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if(cvmx_twsi_wait_iflg(twsi_id)) goto stop;
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/* Write 7-bit addr to twsi_data; set read bit */
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addr.s.slave_addr7 = msg->addr;
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if(is_read) addr.s.r =1;
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else addr.s.r =0;
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stat.s.stat =octeon_twsi_write_byte(twsi_id, addr.u8);
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/* Data read loop */
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if( is_read) {
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/* any status but ACK_RXED means failure - we try to send stop and go idle */
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if(!(stat.s.stat == TWSI_ADDR_R_TX_ACK_RXED)) {
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ret = stat.s.stat;
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msg->len =0;
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goto stop;
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}
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/* We read data from the buffer and send ACK back.
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The last byte we read with negative ACK */
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for(i =0; i<msg->len-1; i++)
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{
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stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 1);
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if(stat.s.stat != TWSI_DATA_RX_ACK_TXED)
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|
goto stop;
|
|
}
|
|
/* last read we send negACK */
|
|
stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 0);
|
|
if(stat.s.stat != TWSI_DATA_RX_NACK_TXED)
|
|
return stat.s.stat;
|
|
} /* read loop */
|
|
|
|
/* Data write loop */
|
|
else {
|
|
/* any status but ACK_RXED means failure - we try to send stop and go idle */
|
|
if(stat.s.stat != TWSI_ADDR_W_TX_ACK_RXED) {
|
|
ret = stat.s.stat;
|
|
msg->len =0;
|
|
goto stop;
|
|
}
|
|
/* We write data to the buffer and check for ACK. */
|
|
for(i =0; i<msg->len; i++)
|
|
{
|
|
stat.s.stat =octeon_twsi_write_byte(twsi_id, msg->buf[i]);
|
|
if(stat.s.stat == TWSI_DATA_TX_NACK_RXED) {
|
|
/* Negative ACK means slave can not RX more */
|
|
msg->len =i-1;
|
|
goto stop;
|
|
}
|
|
else if(stat.s.stat != TWSI_DATA_TX_ACK_RXED) {
|
|
/* lost arbitration? try to send stop and go idle. This current byte likely was not written */
|
|
msg->len = (i-2) >0? (i-2):0;
|
|
goto stop;
|
|
}
|
|
}
|
|
} /* write loop */
|
|
|
|
stop:
|
|
ctl_reg.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
|
|
ctl_reg.s.stp =1;
|
|
ctl_reg.s.iflg =0;
|
|
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
|
|
/* wait for twsi_ctl[stp] to clear */
|
|
cvmx_twsi_wait_stop(twsi_id);
|
|
#if 0
|
|
stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
|
|
if(stat.s.stat == TWSI_IDLE)
|
|
#endif
|
|
/* Leave TWSI core with HLC eabled */
|
|
{
|
|
ctl_reg.u8 =0;
|
|
ctl_reg.s.ce =1;
|
|
ctl_reg.s.enab =1;
|
|
ctl_reg.s.aak =1;
|
|
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|