cbb65b7ec5
On CPUs supporting cmpxchg8b, fetch is performed by cmpxchg8b on corresponding CPU slot, which unconditionally write to the slot. If for that slot, the owner CPU increments it, then both CPUs might run the cmpxchg8b instruction concurrently and this might race and override the incremental write. So the counter update would be lost. Fix it by implementing fetch as IPI and accumulation of result. It is acceptable for rare counter64 fetch operation to be more expensive. Diagnosed and tested by: Andreas Longwitz <longwitz@incore.de> Sponsored by: The FreeBSD Foundation MFC after: 2 weeks |
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